SN8F570211_V2.4_EN (1).pdf- Enhanced 8051 microcon

文件名称: SN8F570211_V2.4_EN (1).pdf

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详细说明：- Enhanced 8051 microcontroller with reduced instruction cycle time (up to 12 times 80C51) - Up to 8 MHz flexible CPU frequency - Internal 32 MHz Clock Generator (IHRC)www.sonix.comtw sn8F5702 Series 1.4 Block Diagram On-chip Debug 8051-based CPu Support ALU Accumulator PC SP, DPTR System Clock and Power Management Reset and power-on ISR 256 Bytes IRAM Controller Controller 32 MHZ IHRC On-chip High Clock Timer ADC 4KB On-chip Non-volatile Memory Generator PWM Generators SPL UART 2C GPIO/ Pin-sharing Controller Copyright C 2019, SONi X Technol ogy Co. Ltd Device overview Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series 2 Table of contents 1 Device overview l垂。。。。音。。;。。l。。自。自。。。“垂非Bc。。自,。。。 2 Table of contents 3 Revision his tory 4 Pin Assignments 5 CPU 6 Special Function Registers.. 20 7 Reset and Power-on Controller 28 8 System Clock and Power Management 35 9 System Operating Mode.......... ∴43 10 nterrupt.… 48 11 GPIO 59 12 External Interrupt..... 13 Timer0 and Timer 1.............................................,............................................................65 14 Timer 2 ,75 15 PWM 16 ADC 要要,,着,D要要着,D ,,着着DD要看着,着DD 92 17UART,…… 鲁自。 103 8SP.,……,……………………………112 1912C 120 20 In-System program .134 21 Electrical characteristics 138 22 Instruction set 141 23 Development Environ ment 146 24 Sn8F5702 Starter-Kit ·…·“· 148 25 ROM Programming pin.……,… 151 26 Ordering Information…… .155 27 Package Intormation……… 157 28 Appendix: Reference document ...... 166 Copyright C 2019, SONi X Technol ogy Co. Ltd Table of contents Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series 3 Revision History Revision Date Description 1.0 Sep 2015 Firstissue 1.1 Oct. 2015 1. Modify timer section and electrical characteristic section 2. Modify SN8F57023/SN8F57024 pin assignment 3. Add program memory security section special function register section and noise filter section 4. Modify minimum requirement in debug interface section 5. Update electrical characteristics 1.2 Nov 20151. Update package type Nov. 20151. SN8F57021 was renamed SN8F570210 2. SN8F57022 was renamed SN8F570200 3. SN&F57023 was renamed SN8F570211 4. SN8F57024 was renamed sn8F570212 1.4 NoV 2015 1. Modify SN8F570200 pin assignment Dec2015 1. Modify electrical characteristic in IHRC section 2. Add power saving description in UART/SPl/12C section 1.6 Apr. 2016 1. Add Timer 2 capture function waveform to illus trate operation 2. Special Function Registers adds Register Declaration section 3. Add Appendix: Reference document chapter. 4. Add ROM Programming Pin chapter 5. Add QFN20 and SoP14 package type. 1.7 Aug2016 1. 12C example modify 2. Modify power Management section and In-System Program section 3. Modify PW1M& PW1YH/L registers description 4. Add SoP& package type 5. Add ADC internal reference range 18 Nov 2016 1. Modify feature table and 12C status code 2. Add UART Baud Rate Table, WdT description in watchdog reset section and QfN16 package type 19 Dec 2016 1. Modify electrical characteristic section. 2.0 Sep 2017 1. Add pin circuit diagrams section 2. Add package information 2.1 NoV 2017 1. Modify LVD related content. 2.2 DeC.2017 11 Add design note description 2.3 Ju.2018 Modify Qfn16 3x 3 dimension Copyright C 2019, SONi X Technol ogy Co. Ltd Revision histo Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series 2. Modify pooC register in UART section 3. Repair an error, omission, etc 4. Add Pin Characteristic section 5. Modify Internal External RAM section description odify program memory section description 7. Modify Configuration of Reset and Power-on Controller section des cription 8. Modify System clock section description 9. Add High Speed Clock and Real time clock section 10. Add System clock timing section 11. Add System Operating Mode chapter. 12. Modify Interrupt Priority section description 13. Interrupt chapter adds example section 14. Modify UaRT chapter des cription and baud rate table 15. 12C chapter adds protocol description diagram and modifies the clock rate table 16. Debug Interface chapter was renamed Development Environment chapter. Modify development Environment chapter description. Add Development Tool section. 17. Add SN5702 Starter-kit chapter 18. Modify RoM Programming Pin chapter description. Add MP5 Hardware Connecting, SN-Link ISP Programming and SN-Link ISP Programming Pin Mapping sections. 19. Update Device Nomenclature section 2.4 Mar 2019 1. Repair an error, omission, etc 2. Modify Pin Circuit Diagrams section Modify t2 Comparison Output section 4. Modify starter-Kit section 5. Modify Package Information section Modify spl operation section description 7. Modify Timer/ Timer1 section description 8. Remove sn8F570212G package type SONIX reserves the right to ma ke change wi thout further not ice to any products he re in to improve reliab il ity function or design. SoNiX does not ass ume any liability arising out of the ap pl ica tion or use of any pro duct or circuit des cr bed he rein; neither does it convey any licens e unde r its patent rights nor the rights of others. SoNIX products are not designed, inte nded, or a uthorized for us as components in systems intended, for surgical implant into the body or other applicat ions intended to support or s ustain life, or for any other application in which the fa il ure of the SONIX product could crea te a situation where personal injury or death may occur. Should Buyer purchase or use SoNIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SoNIX and its officers, employees, subsidiaries, a ffil iates and dis tr ibutors harmless against all claims, cost, dama ges, and expe nses, and reasonable attomey fees arising out of, directly or indirectly any claim of personal injury or death assaciated with s uch uni nte nded or unauthorized use even if s uch claim al le ges that soN IX was negligent re garding the d esign or manufa cture of the part Copyright C 2019, SONi X Technol ogy Co. Ltd Revision History Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series 4 Pin Assignments 4. 1 SN8F5702P/S/T(DIP20/SOP20/TSSOP20) T2 CC0/T2COM0/P002 19P10/AINO/AVREFH/INTO T2CC1/T2COM1/P013 18 P11/AIN1/SWAT SSN/RST/P02 4 17P12/AN2 SCL/T2CC2/T2 COM2/P035 16 P13/AIN3/SCK SDA/T2CC3/T2COM3/P046 15 P14/AIN4/PWM11/MOSI PWM10/UTX/P057 P15/AINS/PWM21/MISO PWM20/URX/P06 8 13|P16/AN6 T2/P079 12|P17/AN7 T2 RL/AIN9/P2010 42SN8F5702(QFN20) 8≌=8 a 2019181716 T2CC1/T2C0M1/P01 15P12/AN2 SCL/T2 CC2/T2COM2/P03 13 P14/AIN4/PWM11/MOSI SDA/T2CC3/T2COM3/P04 4 12 P15/AIN5/PWM21/MISO PWM10/UTX/P055 1P16/AN6 678910 43SN8F570210s(SOP14) 14 VDD T2CCO/ T2 COMO/P0‖2 13P10/AINO/INTO/AVREFH T2CC1/T2COM1/P013 12P11/AIN1/SWAT 1P12/AN2 PWM10/UTX/P055 10P13/AIN3/SCK PWM20/URX/P066 9P14/AIN4/PWM11/MOSI T2/07|7 8P20/AIN9/T2RL Copyright C 2019, SONi X Technol ogy Co. Ltd in Assignments Da tasheet rev 2.4 www.sonix.comtw sn8F5702 Series 44SN8F570211s(S0P14) VSS‖114VDD T2CC0/T2COMO/P002 13P10/AINO/INTO/AVREFH SSN/RSTP02 3 12P11/AIN1/SWAT SCL/T2CC2/T2COM2/P034 11P12/AN2 SDA/T2CC3/T2COM3/P045 10 P13/AIN3/SCK PWM10/UTX/P056 9 P14/AIN4/PWM11/MOSI T2/P077 P20/AIN9/T2RL 45SN8F570213s(SOP14) VDD U 14 VSS T2CC0/T2 COMO/P002 13 P10/AINO/INTO/AVREFH T2CC1/T2COM1/P013 12P11/AIN1/SWAT SSN/RST/PO24 11P12/AN2 PWM10/UTX/P055 10P13/AIN3/SCK PWM20/URX/P056 9 P14/AIN4/PWM11/MOSI T2/P077 8P20/AIN9/T2RL 4.6 SN8F570212S/T(SOP16/TSSOP16 VSS 16VDD T2CC0/T2COM0/PD02 15 P10/AINO/AVREFH/INTO SSN/RST/P02 3 14P11/AIN1/SWAT SCL/T2CC2/T2 COM2/P034 13|P12/AN2 SDA/T2 CC3/T2COM3/P045 12 P13/AIN3/SCK PWM10/UTX/P056 11 P14/AIN4/PWM11/MOSI T2/P077 10P15/AINS/PWM21/MISO T2RL/AIN9/P208 9P16/AN6 47SN8F570200 A(MSOP10) VDD1 U 10P10/AINO/AVREFH/INTO VSS‖2 9P11/AIN1/SWAT T2CC0/T2COM0/P003 8P12/A|N2 SSN/RST/P02 4 7P13/AIN3/SCK PWM10/UTX/P055 6P14/AIN4/PWM11/MOSI 48SN8F570202S(SOP8 VDD1 U vSS T2CCO/T2COM0/P002 7P12/AN2 PWM10/UTX/P053 6P14/AIN4/PWMM11/MOSI INTO/AVREFH/AINO/P104 5P11/AIN1/SWAT Copyright C 2019, SONi X Technol ogy Co. Ltd in Assignments Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series 4. 9 Pin Descriptions Power pins Pin name Type Description VDD Power Power supply VSS Power Ground(o v) Port o Pin name T ype Description P0.0 Digital 1/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-u T2CO M0 Digital Output Timer 2: compare output T2CC0 Digital Input Timer 2: capture O input P0.1 Digital l/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up T2COM Digital Output Timer 2: compare 1 output T2CC1 Digital Input Timer 2: capture 1 input P0.2 Digital I/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters Level change wake-up Reset Digital Input System reset(active low) SSN Digital Input SPl: salve selection pin(slave mode Digital 1/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up T2C0M2 Digital Output Timer 2: compare 2 output T2CC2 Digital Input Timer 2: capture 2 input. SCL Digital 1/0 12C: clock output(master) clock input (slave) Digital I 0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up T2C0M3 Digital Output Timer 2: compare 3 output T2CC3 Digital Input Timer 2: capture 3 input SDA Digital I/0 12C: data pin P0.5 Digital 1/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up UTX Digital Output UART: transmission pin PWM1O Digital Output PWM: programmable PWM output P0.6 Digital 1/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up URX Digital Input UART: reception pin PWM20 Digital Output PWM: programmable PWM output Copyright C 2019, SONi X Technol ogy Co. Ltd in Assignments Da tas heet rev. 2. 4 www.sonix.comtw sn8F5702 Series P0.7 Digital l/0 GPIO: Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up T2 Digital Input Timer 2: event counter input Port 1 Pin name Type Description P1.0 Digital I/o Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up AINO Analog Input ADC: input channel 0 INTO Digital Input INTO: external interrupt 0 AVREFH Analog Input ADC: external reference voltage P1.1 Digital l/0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up AIN1 Analog Input ADC: input channel 1 SWAT Digital l/0 Debug interface P1.2 Digital I 0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters Level change wake-up AIN Analog Input ADC: input channel 2 P1.3 Digital I/0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up ain Analog Input ADC: input channel 3 SCK Digital I/0 SPl: clock output(master) clock input(slave) P1.4 Digital l/0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters Level change wake-up an4 Analog Input ADC: input channel 4 MOSI Digital I/0 SPl: transmission pin(master)reception pin(slave) PWM11 Digital Output PWM: programmable PWM output P1.5 Digital Iy0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up AIN Analog Input ADC: input channel 5. MISO Digital I/0 SP reception pin (master)trans mission pin (slave) PWM21 Digital Output PWM: programmable PWM output. P1.6 Digital l/0 Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up ain Analog Input ADC: input channel 6 P1.7 Digital I/o Bi-direction pin. Schmitt trigger structure as input mode Built-in pull-up resisters. Level change wake-up AINZ Analog Input ADC: input channel 7. Copyright C 2019, SONi X Technol ogy Co. Ltd in Assignments Da tas heet rev. 2. 4 10

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