sx1213数据手册.pdfSX12113是Semtech的集成UHF频段接收器。SX1213用于4

文件名称: sx1213数据手册.pdf

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详细说明：SX12113是Semtech的集成UHF频段接收器。SX1213用于433MHz频段，其它各参数完全与1210相同且管脚兼容。SX1213的接收电流不到3mA，为业界最低，与竞争对手相比，接收电流要低6倍。设计应用于无线报警器、安全，家庭自动化中的传感器网络，以及自动化抄表领域。该器件支持FSK数据速率为1.56~200kbps，OOK数据速率高达32kbps。25kbps时FSK调制的接收器灵敏度为 -107dBm；2kbps时OOK接收器灵敏度为-113dBm。此外，该芯片符合欧洲(ETSI EN 300-220 V2.1.1)和南美(FCC Part 15.247和15.249)规范SEMECH Figure 1: SX121 3 Simplified Block Diagram Figure 27: Continuous Mode conceptual view Figure 2: SX1213 Pin Diagram Figure 3: SX1213 Detailed Block Diagrar 5623 Figure 28: Rx Processing in Continuous Mode Figure 29: uC Connections in Continuous Mod Figure4: Power Supply Breakdown.….… Figure 30: Buffered Mode Conceptual view Figure 5: Frequency Synthesizer Description Figure 31: Rx Processing in Buffered Mode(FIFO size=16,.39 Figure 6: LO Generator.... Fifo fill method=0) Figure 7: Loop Filter 6 Figure 32: uC Connections in Buffered Mode 41 Figure 8: Receiver Architecture 8 Figure 33: Packet Mode Conceptual View Figure: FSK Receiver Setting….......……,18 Figure 34: Fixed Length Packet Format.......... A.gure 10 OOK Receiver Setting Fi 18 Figure35: Variable Length Packet Format.…… igure 11: Active Channel Filter Description.. 19 Figure 36: CRC Implementation Figure 12: Butterworth Filter's Actual BW Figure 37: Manchester Decoding Figure 13: Polyphase Filters Actual BW Figure 38: Data Whitening Implementation.. Figure 14: RSSI Dynamic Range Figure 39: uC Connections in Packet Mode Figure 15: RSSI IRQ Timings Figure 40: Optimized Rx Cycle Figure 16: OOK Demodulator Description Figure 41: Rx Hop Cycle Figure 17: Floor Threshold optimization Figure 42: POR Timing Diagram Figure 18: BitSync Description Figure 19: SX1213's Data Processing Conceptual View 690 Figure 43: Manual Reset Timing Diagram Figure44: Reference Design Circuit Schematic..………….61 Figure 20: SPl Interface Overview and uC Connections Figure 45: Reference Design's Stackup Figure 21: Write Register Sequence.. Figure 46: Reference Design Layout(top view) Figure22: Read Register Sequence………… Figure 23 Read Bytes Sequence (ex: 2 bytes/ 32 Figure 47: Package Outline Drawing Figure 48: PCB Land Pattern 64 Figure 24: FIFO and Shift Register (SR) Figure 49: Tape Reel Dimensions 64 Figure 25: FIFO Threshold IRQ Source Behavior Figure 26: Sync Word recognition 344 Rev2-Jy15,2009 Page 3 of 65 www.semtech.com SEMECH Table 1: Ordering Information... Table 16: Relevant Configuration Registers in Continuous Mode Table 2: SX1213 Pinouts (data processing related only) Tabe3: Absolute Maximum Ratings…...,… Table 17: Interrupt Mapping in Buffered Rx and Stby Modes .. 40 Table 4: Operating Range 78889 Table 18: Relevant Configuration Registers in Buffered Mode( data Table 5: Power consumption Specification processing related only)…… Table 6: Frequency Synthesizer Specification Table 19: Interrupt Mapping in Rx and Stby in Packet Mode.. 47 Table 7: Receiver Specification Table 20: Relevant Configuration Registers in Packet Mode(data Table 8: Digital Specification (1) ..11 processing related only) T able 9: MCParam Freq_ band and MCParam Subband setting Table 21: Registers List Table 22: MCParam Register Description Table 10: Operating Modes Table 23: IRQParam Register Description Table 11: Pin Configuration vs chip Mode Table 24: RXParam Register Description Table 12: Data Operation Mode selection Table 25: SYNCParam Register Description Table 13: Config VS Data SPI Interface Selection Table 26: OSCParam Register Description Table 14: Status of FIFO when Switching Between Different Table 27: PKTParam Register Description Modes of the Chip Table 28: Crystal Resonator Speci 57 Table 15: Interrupt Mapping in Continuous RX Mode Table 29: Reference Design bd fication Table 30: Tools Ordering Information BOM Bill of materials Local oscillator BR Bit rate LSB Least significant bit BW Bandwidth MSB Most Significant Bit CCITT Comite consultatif international NRZ Non return to zero Telephonique et telegraphique -ITU NZF Near Zero Intermediate Frequency CP Charge Pump OOK On Off Keying CRC Cyclic Redundancy Check PA Power Amplifie DAC Digital to Analog Converter PCB Printed Circuit Board DDS Direct Digital Synthesis PFD Phase Frequency Detector DLL ynamically Linked Library PLL Phase-Locked Loop ERP Equivalent Radiated Power European telecommunications standards POR Power on reset ETS Institute RBW Resolution bandwidth FCC Federal communications Commission RF Radio Frequency Frequency Deviation RSSI Received Signal Strength Indicator FIFO First In first out Rx Receiver FS Frequency Synthesizer SAW Surface Acoustic Wave FSK Frequency Shift Keying SPI Serial Peripheral Interface GUI Graphical User Interface SR Shift Register C Integrated Circuit Stby Standby D IDentificator TX Transmitter F Intermediate Frequency Microcontroller IRQ Interrupt ReQuest VcO oltage Controlled Oscillator ITU International telecommunication Union XO Crystal Oscillator LFSR Linear Feedback Shift Register XOR eXclusive or LNA Low Noise Amplifier Rev2-Jy15,2009 Page 4 of 65 www.semtech.com SEMECH This product datasheet contains a detailed description of the sX1213 performance and functionality. Please consult the Semtech website for the latest updates or errata The sX1213 is a single chip FSK and ooK receiver capable of operation in the 300 to 510 MHz license free ISM frequency bands. It complies with both the relevant European and North American standards, EN 300-220 V2 1.1 (June 2006 release) and FCC Part 15(10-1-2006 edition). A unique feature of this circuit is its extremely low current consumption in full active mode of only 3mA (typ). The sX1213 is available in a 5x5 mm TQFN-32 package RSSI OOK De Digital Filtering/ Demodulate 图LNA 1st Stage IF/Gai 2nd Stage Mixers Mixers Q Amplification FFSK Demod CLKOUT DATA Control LO1 RX Sync word Frequency PLL PLL LOCK Synthesis (Comparator, VcO Filter, Dividers) LO2 R FIFC Post demod XTAL Loop Filter Rev2-Jy15,2009 Page 5 of 65 www.semtech.com SEMECH The following diagram shows the pins arrangement of the QFN package, top view ♀臣舀g熙g§呂 8日R将月 1 TEST5 10 GND 24 TEST2 2 TEST1 2 PLL LOcK 3 VR VCO 7:sX1213 22RQ1 4 VCD M 21|RQ0 www 20 DATA 6 LF M 19 CLKOUT 7 LF P 18 SCK 8 TEST6 17 MOs Dimensions: 5 mm x 5 mm Lead pitch: o5 mm Le ads centered on package Note Pin0= GROUND. located经 on the underside of the package 面的是 Notes yyww refers to the date code refers to the lot number Rev2-Jy15,2009 Page 6 of 65 www.semtech.com SEMECH GND Exposed ground pad TEST5 l/O Connect to gnd 0123456789 TEST1 v/O Connect to gnD VR_VCO Regulated supply of the Vco VCO M VcO tank VCO P vO VcO tank LF M vO PLL loop filter LE P v/O PLL loop filter TEST6 v/O Connect to gnd TESTi v/O Connect to gnD 10 XTAL P vO Crystal connection 11 XTAL M vO Crystal connection 12 TESTO Connect to gnD 13 Tests /O POR. Do not connect if unused 14 NSS_CONFIG SPI CONFIG enable 15 NSS DATA SPI DATA enable 16 MISO sPl data output 17 MOSI SPI data input 18 SCK SPI clock input 19 CLKOUT Clock output DATA nrZ data output(Continuous mode) IRQ O Interrupt output IRQ 1 Interrupt outpu PLL LOCK PLL lock detection output TEST2 Connect to gnd 25 TEST3 vO Connect to gnd 26 VDD Supply voltage 27 VR 1V O Regulated supply of the analog circuitry 28 VR DIG ● Regulated supply of digital circuitry 29 NC onnect to gnd TEST4 v/O Connect to gnD 31 RF input NC Connect to gnd Note: pin 13 Test 8) can be used as a manual reset trigger. See section 7. 4.2 for details on its use Rev2-Jy15,2009 Page 7 of 65 www.semtech.com SEMECH The SX1213 is a high performance radio frequency device. It satisfies Class 2 of the JEdEC standard JESD22-A1 14-B(Human Body Model), except on pins 3-4-5-27-28-31-where it satisfies class 1A Class Ill of the JEDEC standard JESD22-C101C(Charged Device Model)on all pins It should thus be handled with all the necessary ESD precautions to avoid any permanent damage Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability VDDmr Supply voltage -0.337 V Tmr Storage temperature 125 Pmr Input level 0 dBm VDDop Supply Voltage 2.1 3.6 Trop Temperature 40+85C Input Level 0dBm Conditions: Temp 25C, VDd=3.3 V, crystal frequency =12.8 MHz, carrier frequency =315 or 434 MHZ, modulation FSK, data rate=25 kb/s, Fdev 50 kHz, fc= 100 kHz, unless otherwise specified IDDSL Supply current in sleep mode 0.1 2 IDDST Supply current in standby mode clKout disabled Crystal oscillator running 95 JA IDDES Supply current in FS mode Frequency synthesizer 13 1.7 runnIng IDDR Supply current in receiver mode 3.0 3.5 mA Information from design and characterization Rev2-Jy15,2009 Page 8 of 65 www.semtech.com SEMECH MHZ 350 MHZ Programmable(may FR 350 390 MH Frequency ranges require 430 specific BOM) 390 MHZ 430 470 MH 470 510 MHz BR F Bit rate(FSK) NRZ 1.56 200 Kb/s BR O Bit rate(OOK) NRZ 156 32 Kb/s FDA Frequency deviation(FSK) 33 50 200 KHz XTAL I Crystal oscillator frequency 12.8 15 MHZ FSTEP Frequency synthesizer Variable, depending on the 2 KHz step frequency. Oscillator wake-up time From Sleep mode ms Frequency synthesizer TS FS wake-up time at most From Stby mode 500 10 kHz away from the 800 target 200 kHz step 180 1 MHz step 200 Frequency synthesizer hop/5 MHz step 250 TS HOP time at most 10 kHz away 7 MHz step 260 us from the target 12 MHz step 290 s 20 MHZ step 320 s 27 MHz step 340 us nformation from design and characterization Rev2-Jy15,2009 Page 9 of 65 www.semtech.com SEMECH On the following table, fc and fo describe the bandwidth of the active channel filters as described in section 3.3.4.2. All sensitivities are measured receiving a Pn15 sequence, for a bER of 0.% 434 MHz. BR=25 kb/s Fdev =50 kHz. fc=100 kH -104 dBm RES F Sensitivity(FSK) 434 MHz. 2kb/s nrz -110 dBm fc-fo=50 kHz. fo=50 khz RFS O Sensitivity(ooK) CCR Co-channel rejection Modulation as wanted signal -12 d Bc Offset 300 kHz. unwanted tone is not modulated 27 dB ACR Adjacent channel Offset 600 kHz. unwanted 52 dB rejection tone is not modulated Offset =1.2 MHz. unwanted 57 dB tone is not modulated Offset 1 MHz -48 d Bm unmodulated Blocking immunity Offset= 2 MHz -37 dBm unmodulated. no saw Offset= 10 MH -33 d Bm unmodulated. no saw RXBW F(1,2) Receiver bandwidth in Single side BW Polyphase Off 50 250 FSK mode RXBW O(1,2) Receiver bandwidth in Single side BW Polyphase On 50 OoK mode 400 lP3 Input 3 order intercept Interferers at 1MHz and dBm point 1.950 MHz offset TS RE Receiver wake-up time From FS to Rx ready 280 500 ' S RE2 Receiver wake-up time from Stby to Rx ready 600 900 200 kHz step 400 1MHz step 400 Receiver hop time from 5MHz step 460 TS_RE_HOP RX ready to Rx ready with 7MHz step A8 0 s a frequency hop 12MHz step 520 s 20MHz step s 27MHz step 600 Is TS RSSI RSSI sampling time From Rx ready 1/Fde「s DR RSSI RSSI dynamic Range Ranging from sensitivity 70 dB Information from design and characterization (2)This reflects the whole receiver bandwidth as described in sections 3.3 4.1 and 3.3.4.2 Rev2-Jy15,2009 Page 10 of 65 www.semtech.com

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