sx1212数据手册.pdfSX12112是Semtech的集成UHF频段接收器。SX1212用于8

文件名称: sx1212数据手册.pdf

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详细说明：SX12112是Semtech的集成UHF频段接收器。SX1212用于868MHz、915MHz频段，其它各参数完全相同且管脚兼容。SX1212的接收电流不到3mA，为业界最低，与竞争对手相比，接收电流要低6倍。设计应用于无线报警器、安全，家庭自动化中的传感器网络，以及自动化抄表领域。该器件支持FSK数据速率为1.56~200kbps，OOK数据速率高达32kbps。25kbps时FSK调制的接收器灵敏度为 -107dBm；2kbps时OOK接收器灵敏度为-113dBm。此外，该芯片符合欧洲(ETSI EN 300-220 V2.1.1)和南美(FCC Part 15.247和15.249)SEMECH Figure 1: SX1212 Simplified Block Diagram Figure 33: Sync Word Recognition .40 Figure2:S×1212 Pin Diagran… 6 Figure 34: Continuous Mode conceptual view Figure3:s×1212 Detailed Block Diagram… Figure 35: Tx Processing in Continuous Mode Figure 4: Power Supply Breakdown Figure 36: Rx Processing in Continuous Mode Figure 5: Frequency Synthesizer Description Figure 37: uC Connections in Continuous mode 4444 Figure 6: LO Generator Figure 38: Buffered Mode Conceptual view Figure7: Loop Filter……… 16 Figure 39: Tx processing in Buffered Mode(FIFo size =16, Figure 8: Transmitter Architecture 18 T× start irq_0=0 Figure 9: I(t), Q(oVerview Figure 40: Rx Processing in Buttered Mode(FIFo Size=16 Figure 10: PA Control 21 Fifo fill method=0) Figure 11: Optimal Load Impedance Chart Figure 41: uC Connections in Buffered Mode Figure 12: Recommended PA Biasing and Output Matching igure 42: Packet Mode Conceptual View Figure 13: Front-end Description Figure 43: Fixed Length Packet Format Figure 14: Receiver Architecture Figure 44: Variable Length Packet Format Figure 15: FSK Receiver Setting Figure 45: CRC Implementation Figure 16: OOK Receiver Setting 23 Figure 46: Manchester Encoding/Decoding Figure 17: Active Channel Filter Description Figure 47: Data Whitening Figure 18: Butterworth Filter's Actual BW 26 Figure 48: uC Connections in Packet Mode.........55 Figure 19: Polyphase Filter's Actual BW 26 Figure 49: Optimized Rx cycle .67 Figure 20: RSSI Dynamic Range Figure 50: Optimized Tx Cycle 68 Figure 21: RSSI IRQ Timings 28 Figure 51: Tx Hop Cycle Figure 22: OOK Demodulator Description Figure 52: RX Hop Cycle 70 Figure23: Floor Threshold Optimization…… Figure53:Rx→Tx÷ Rx Cycle Figure 24: BitSync Description Figure 54: POR Timing Diagram Figure 25: SX1212's Data Processing conceptual view 34 Figure 55: Manual Reset Timing Diagram Figure 26: SPI Interface Overview and uC connections Figure 56: Reference Design Circuit Schematic Figure 27: Write Register Sequence 36 Figure 57: Reference Design's Stackup 74 Figure 28: Read Register Sequence 37 Figure 58: Reference Design Layout( top view Figure 29: Write Bytes Sequence(ex: 2 bytes) 37 Figure59: Package Outline Drawing…………… 75 Figure 30: Read Bytes Sequence(ex: 2 bytes) Figure 60: PCB Land Pattern Figure 31: FIFo and shift Register (SR) 38 Figure 61: Tape Reel Dimensions Figure32: FIFO Threshold IRQ Source Behavior…………….39 Rev 2-June 1 8th 2009 Page 3 of 77 www.semtech.com SEMECH Table 1: Ordering Information... Table 19: Relevant Configuration Registers in Continuous Mode Table 2: SX1212 Pinouts (data processing related only Table 3: Absolute Maximum Ratings 8 Table 20: Interrupt Mapping in Buffered Rx and Stby Modes... 46 Table 4: Operating Range Table 21: Interrupt Mapping in Tx Buffered Mode Table 5: Power Consumption Specification Table 6: Frequency Synthesizer Specification 88990 Table 22: Relevant Configuration Registers in Buffered Mode(data processing related only)…… Table 7: Transmitter Specification Table 23: Interrupt Mapping in Rx and Stby in Packet Mode..55 Table 8: Receiver Specification Table 24: Interrupt Mapping in Tx Packet Mode T able 9: Digital Specification Table 25: Relevant Configuration Registers in Packet Mode(data Table 10: MCParam Freq band Setting processing related only Table 11: Pa rise/fall times Table 26: Registers list 5688 Table 12: Operating Modes 335 Table 27: MCParam Register Description Table 13: Pin Configuration Vs Chip Mode Table 28: IRQParam Register Description Table 14: Data Operation Mode selection Table 29: RXParam Register Description Table 15: Config vS Data SPI Interface Selection Table 30: SYNCParam Register Description Table 16: Status of FIFO when Switching Between Different Table 31: TXParam Register Description Modes of the Chip Table 32: OSCParam Register description 6 Table 17: Interrupt Mapping in Continuous Rx mode Table 33: PKTParam Register Description 65 Table 18: Interrupt Mapping in Continuous Tx Mode Table 34: Crystal Resonator Specification 66 Table 35: Reference Design BOM... 74 BOM Bill of materials Local oscillator BR Bit rate LSB Least Significant Bit BW Bandwidth MSB Most Significant Bit CCITT Comite consultatif internationa NRZ Non return to zero Telephonique et telegraphique -ITU NZF Near Zero Intermediate Frequency CP Charge Pump OOK On Off Keying CRC Cyclic Redundancy Check PA Power Amplifier DAC Digital to Analog Converter PCB Printed Circuit board DDS Direct Digital Synthesis PFD Phase Frequency Detector DLL Dynamically Linked Library PLL Phase-Locked Loap ERP quivalent radiated Power PO Power on reset ETS European Telecommunications Standards DR Institute RBW Resolution bandwidth FCC Federal communications commission RF Radio Frequency Fdev Frequency Deviation RSS Received Signal Strength Indicator FIFO First In first out RX Receiver FS Frequency Synthesizer SAW Surface Acoustic Wave FSK Frequency Shift Keying SPI Serial Peripheral Interface GUI Graphical User Interface SR Shift Registe C Integrated Circuit Stby Standb D IDentificator Transmitter F Intermediate Frequency Microcontroller IRQ Interrupt ReQuest VcO Voltage Controlled Oscillator ITU International telecommunication Union XO Crystal Oscillator LFSR Linear Feedback Shift Register XOR eXclusive or LNA Low Noise Amplifier Rev 2-June 1 8th 2009 Page 4 of 77 www.semtech.com SEMECH This product datasheet contains a detailed description of the sX1212 performance and functionality. Please consult the Semtech website for the latest updates or errata The SX1212 is a single chip FSK and ooK transceiver capable of operation in the 300 to 51OMHz license free ISM frequency bands. It complies with both the relevant European and North American standards, EN 300-220 V2 1.1 (June 2006 release) and FCC Part 15(10-1-2006 edition). A unique feature of this circuit is its extremely low current consumption in receiver mode of only 3mA (typ) The sX1212 comes in a 5x5 mm TQFN-32 package Transmission Phaso-ah to frequancy ah 2 nd stag日 1st Stage Modulation earrvari'on(FBK Mada M HOoS, DACs, KEE Q Q IneptaOt 01T on RSSI coκ DarTed Digital Demodulator LNA 1st Stage H-IF Gait +-2nd Stage Filtering Mixers adi FSK DITKA CLKOUT Mixers DETA Control C Ri Lo2 i Sync word equency PLL 卡L7 F凵LLoK Synthesis 上 ampara veo Fter, Dividers) FIFg Post Demod XTAL Dop Fle Rev 2-June 1 8th 2009 Page 5 of 77 www.semtech.com SEMECH The following diagram shows the pins arrangement of the QFN package, top view β望g 1 TEST5 24 TEST2 10 GND 2 TEST1 23 PLL LOCK 3 VR VCO 22|RQ_1 4 VCO M 二21RQo yyww 5 VCO P 20 DATA 6 LE M 1 9 CLKOUT 7 LF P 18 SCK u 8 TEST6 17 MOSI Dimensions. 5 mm x 5 mm Lead Pitch: 0.5 mm (Leads centered on package) Note pino- GRoUND located on the underside of the package 11002p0 Notes: yyww refers to the date code --- refers to the lot number Rev 2-June 1 8th 2009 Page 6 of 77 www.semtech.com SEMECH 0 GND Exposed ground pad TEST5 l/O Connect to gnd TEST1 v/O Connect to gnD 3 VR_VCO Regulated supply of the Vco 4 VCO M VcO tank VCO P vO VcO tank LF M vO PLL loop fil LE P v/O PLL loop filter 8 TEST6 v/O Connect to gnd TESTi v/O Connect to gnD 10 XTAL P vO Crystal connection 11 XTAL M vO Crystal connection 12 TESTO Connect to gnD 13 Tests /O POR. Do not connect if unused 14 NSS_CONFIG SPI CONFIG enable 15 NSS DATA SPI DATA enable 16 MISO sPl data output 17 MOSI SPI data input 18 SCK SPI clock input 19 CLKOUT Clock output DATA vO nrZ data input and output(Continuous mode) IRQ O Interrupt output IRQ 1 Interrupt outpu PLL LOCK PLL lock detection output 24 TEST2 No connect 25 TEST3 vO Connect to gnd 26 VDD Supply voltage 27 VR 1V O Regulated supply of the analog circuitry 28 VR DIG ● Regulated supply of digital circuitry 29 VR PA Regulated supply of the PA TEST4 v/O Connect to gnd 31 RFIO /O INput/output NC Connect to gnd Note: pin 13 Test 8) can be used as a manual reset trigger. See section 7. 4.2 for details on its use Rev 2-June 1 8th 2009 Page 7 of 77 www.semtech.com SEMECH The SX1212 is a high performance radio frequency device. It satisfies Class 2 of the JEdEC standard JESD22-A114-B (Human Body Model), except on pins 3-4-5-27-28-29-31 Where it satisfies class 1A Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability VDDmr Supply voltage Tmr Storage temperature 55 125 Pmr Input level 0 dBm VDDop Supply Voltage 2.1 3.6 Trop Temperature 40 +85C ML Input Leve 0 dBr Conditions: Temp= 25C, VDd = 3.3 V, crystal frequency =12.8 MHz, carrier frequency =434 MHz, modulation FSK, data rate= 25 kb/s, Fdev=50 kHz, fc= 100 kHz, unless otherwise specified IDDSL Supply current in sleep mode 0.1 2 UA IDDST Supply current in standby mode clKout disabled Crystal oscillator running 65 85 A IDDES Supply current in FS mode Frequency synthesizer 1.3 1.7 A runnIng IDDR Supply current in receiver 3.0 3.5 mode 25 30 MA IDDT Supply current in Output power =+10 dBm transmitter mode Output power= 1dBm 16 21 mA 1) Guaranteed by design and characterization Rev 2-June 1 8th 2009 Page 8 of 77 www.semtech.com SEMECH 300 330 MHZ 350 MHZ FR Programmable 350 390 MH Frequency ranges (may require specific BOM) 390 430 MHZ 430 470 MH 470 510 MH BR F Bit rate(FSK) NRZ 0.78 150 Kb/s BR O Bit rate(OOK) NRZ 0.78 32 Kb/s FDA Frequency deviation(FSK) 33 50 200 KHz XTAL I Crystal oscillator frequency 12.8 15 MHZ FSTEP Frequency synthesizer Variable, depending on the 2 KHz step frequency. Oscillator wake-up time From Sleep mode ms Frequency synthesizer TS FS wake-up time at most 10 kHz away from the From Stby mode 500 800 target 200 kHz step 180 1 MHz step 200 Frequency synthesizer hop/5 MHz step 250 TS HOP time at most 10 kHz away 7 MHz step 260 us from the target 12 MHz step 290 s 20 MHZ step 320 s 27 MHz step 340 us Guaranteed by design and characterization RF output power, Maximum power setting +12.5 d Bm RFOP programmable with 8 steps of typ. 3dB Minimum power setting -8.5 d Bm Measured with a 600 kHz PN Phase noise offset at the transmitter 112 d Bc/hz output At any offset between SPT Transmitted spurious 200 kHz and 600 kHz unmodulated carrier Fdev 47 d Bc 50 kH TS TR Transmitter wake-up time From FS to Tx ready 120 500 us 'S TR2 Transmitter wake-up time From Stby to Tx ready. 600900μs Guaranteed by design and characterization Rev 2-June 1 8th 2009 Page 9 of 77 www.semtech.com SEMECH On the following table, fc and fo describe the bandwidth of the active channel filters as described in section 3. 4.4.2 All sensitivities are measured receiving a Pn15 sequence, for a ber of o.% 434 MHz. BR=25 kb/s Fdev =50 kHz. fc=100 kH -104 dBm RES F Sensitivity(FSK) 434 MHz. 2kb/s nrz -110 dBm fc-fo=50 kHz. fo=50 khz RFS O Sensitivity(ooK) CCR Co-channel rejection Modulation as wanted signal -12 d Bc dB ACR Adjacent channel Offset=300 kHz Offset 600 kHz 42 dB rejection Offset=1.2 MHz Offset= 1 MHz 53 dBc unmodulated blocking immuni Offset=2 MHz unmodulated. no saw Offset= 10 MHz unmodulated. no saw RXBW Fl12) Receiver bandwidth in Single side BW FSK mode Polyphase Off 50 250 k卜 RXBW O(1,2) Receiver bandwidth in Single side BW OoK mode Polyphase On 50 400 z lP3 Input 3 order intercept Interferers at 1 MHz and 1.950 MHz offset 28 dBm poIn TS RE( Receiver wake-up time From Fs to Rx ready 280 500 'S RE2 Receiver wake-up time From Stby to Rx ready 900 200 kHz ste 400 1MHz step 400 ps Receiver hop time from 5MHZ step 460 TS_RE_HOP RX ready to RX ready with 7MHz step 480 a frequency hop 12MHz step 520 20MHz step 550 us 27MHz step 600 'S_RSSI RSSI sampling time From Rx ready I 1/Fdev s DR RSSI RSSI dynamic Range Ranging from sensitivity 70 dB Information from design and characterization (2)This reflects the whole receiver bandwidth as described in sections 3.4.4.1 and 3.4.4.2 Rev 2-June 1 8th 2009 Page 10 of 77 www.semtech.com

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