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RISCv 非特权指令集规范，介绍IFMAD标准扩展，32位及64位，2019.6.8日更新。Preface
This document describes the risc-v unprivileged architecture
The rvWMO memory model has been ratified at this time. The ISa modules marked Ratified, have
bccn ratified at this timc. Thc modules marked Frozen arc not cxpcctcd to change significantly
before being put up for ratification. The modules marked Draft are expected to change before
ratification
The document contains the following versions of the RISC-V ISA modules
B
Version Status
RVWMO 2.0
Ratified
Rⅴ32I2.1
Ratified
R64
1
211
Ratified
RV32E
Draft
RV1281
7
Draft
ExtensionⅤ ersion S
Zifencei 2.0
Ratified
Z
2.0
Ratified
M
Ratified
A
F
F
Q
Zts
Counters
2922220200
Ratify
2
Ratified
2
Ratified
Ratified
Frozen
0
Draft
.0
t
B
0
Dne批t
T
000010
0
lft
2
Draft
V
Draft
1
Drawl
Za
Draft
The changes in this version of the document include
Moved description to Ratified for the ISa modules ratified by the board in early 2019
Volume I: RISC-V Unprivileged IsA v20190608-Base-Ratified
o Removed the a extension from ratification
. Changed document version scheme to avoid conlusion with versions of the Isa nodules
Incremented the version numbers of the base integer ISA to 2. 1, reflecting the presence of the
ratified RVWMO memory model and exclusion of FENCE. I, counters, and CSr instructions
Chat were in previous base ISa
Incremented the version numbers of the F and d extensions to 2.2, reflecting that version 2.1
changed the canonical NaN, and version 2.2 defined the NaN-boxing scheme and changed the
delinition of the fmin and fmax instructions
Changed name of document to refer to"unprivileged"instructions as part of move to separate
ISA specifications from platform profile mandates
e Added clearer and more precise definitions of execution environments, harts traps and mem-
ory accesses
Defined instruction-set categories: standard, reserved, custom, non-standard, and non
con.g
Removed text implying operation under alternate endianness, as alternate-endianness opera-
tion has not yet been defined for RIsC-V
Changed description of misaligned load and store behavior. The specification now allows
visible misaligned address traps in execution environment interfaces, rather than just man-
dating invisible handling of misaligned loads and stores in user mode. Also, now allows
access exceptions to be reported for misaligned accesses(including atomics) that should not
be emulated
Moved FENCE. I out of the mandatory base and into a separate extension, with Zifencei Isa
name. FENCE. I was removed from the Linux user ABi and is problematic in implementations
with large incoherent instruction and data caches. However, it remains the only standard
instruction-fetch coherence mechanism
Removed prohibitions on using RV32F with other extensions
Removed platform-specific mandates that certain encodings produce illegal instruction ex
ceptions in RV32E and Rv611 chapters
Counter/timer instructions are now not considered part of the mandatory base ISA, and
sO CSR instructions were moved into separate chapter and marked as version 2.0, with the
unprivileged counters moved into another separate chapter. The counters are not ready for
ratification as there are outstanding issues, including counter inaccuracies
A CSR-access ordering model has been added
Explicitly defined the 16-bit half-precision Hoating-point format for floating-point instructions
in the 2-bit fmt field.
Defined the signed-zero behavior of Fminfmt and FMAXfmt, and changed their behavior on
signaling-NaN inputs to conform to the minimumNumber and maximum Number operations
in the proposed IEEE 754-201x specification
The memory consistency model, RVWMO, has been defined
The "Zam"extension, which permits misaligned AMOs and specifies their semantics, has
been defined
The"Ztso"extension, which enforces a stricter memory consistency model than RVWMO
has been defined
Improvements to the description and commentary
Defined the term alIgN as shorthand to describe the instruction-address alignment con-
straint
Volume I: RISC-V Unprivileged Isa v20190608-Base-Ratified
Removed text of p extension chapter as now superceded by active task group documents
Renoved text of V extension chapter as now superceded by separate veclor extension drall
document
Preface to Document Version 2.2
This is vcrsion 2.2 of thc document describing thc RISC-V uscr-lcvcl architecture. The document
contains the following versions of the RISC-V ISA modules
B
ase
Version draft Frozen
RⅤ32I2.0
RV32E1.9
RV64I2.0
YNYN
RV128I1.7
Extension Version
Frozen?
2.0
2.0
MAFDOLCBJTPV
2.0
2.0
2.0
02
00
0.0
0000
00171
YYYYNYNNNNNN
To date, no parts of the standard have been officially ratified by the rIsC-V Foundation, but
the components labeled "frozen"above are not expected to change during the ratification process
beyond resolving ambiguities and holes in the specification
The major changes in this version of the document include
The previous version of this document was released under a Creative Commons Attribution
41.0 International license by the original authors, and this and future versions of this document
will be released under the same license
o Rearranged chapters to put all extensions first in canonical order
Improvements to the dcscription and commentary
Modified implicit hinting suggestion on jalR to support more efficient macro-op fusion of
LUI/JALR and AUIPC/JALR pairs
e Clarification of constraints on load-reserved /store-conditional sequences
A ncw tablc of control and status registor(CSr)mappings
Clarified purpose and behavior of high-order bits of fcsr
Volume I: RISC-V Unprivileged IsA v20190608-Base-Ratified
Corrected the description of the FNmaDifmt and FNMSUB fmt instructions, which had
suggested the incorrect sign of a zero result
Instructions FMvS X and FmvXs were renamed to FMvW. X and FMvX w respectively
to be more consistent with their semantics, which did not change. The old names will continue
to be supported in the tools
Specified behavior of narrower (64 bits to avoid moving the rd specifier in very
long instruction formats
CSr instructions are now described in the base integer format where the counter registers
are introduced, as opposed to only being introduced later in the floating-point section(and
the companion privileged architecture manual
. The SCaLL and sbreak instructions have been renamed to ecall and ebreak. re
spectively. Their encoding and functionality are unchanged
Clarification of Hoating -point NaN handling and a new canonical nan value
Clarification of values returned by floating-point to integer conversions that overflow.
Clarification of LR/SC allowed successes and required failures, including use of compressed
instructions in the sequence
A new RV32E base ISa proposal for reduced integer register counts, supports MAC
exten
SIons
a revised calling convention
Relaxed stack alignment for soft-float calling convention, and description of the r.v32E calling
convcntion
A revised proposal for the C compressed extension, version 1.9
Volume I: RISC-V Unprivileged Isa v20190608-Base-Ratified
Preface to version 2.0
This is the second release of the user ISA specification, and we intend the specification of the
base user ISa plus general extensions (i.e. IMAFD)to remain fixed for future development. The
Tollowing changes have been made since Version 1.0 24 of this ISA specificalion
The Isa has been divided into an integer base with several standard extensions
The instrucTion formals have been rearranged to Inake iImInediale encoding Imore ellicienl
The base Isa has been defined to have a little-endian memory system, with big-endian or
bi-endian as non-standard variants
Load-Reserved /Store-Conditional(LR/SC) instructions have been added in the atomic in-
struction extension
e AMOs and LR/sC can support the release consistency model
The FENCE instruction provides finer-grain memory and I/O orderings
An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP
has been changed to make room
The AUIPC instruction, which adds a 20-bit upper immediate to the PC, replaces the RDNPC
instruction, which only read the current PC value. This results in significant savings for
position-independent code
The JAL instruction has now moved to the U-Type format with an explicit destination
register, and the instruction has been dropped being replaced by jal with rd=xo. this
removes the only instruction with an implicit destination register and removes the j-Type
instruction format from the base ISA. There is an accompanying reduction in JAL reach, but
a significant reduction in base ISA complexity
The static hints on the JALR instruction have been dropped. The hints are redundant with
the rd and rsl register specifiers for code compliant with the standard calling convention
The JALR instruction now clears the lowest bit of the calculated target address, to simplify
hardware and to allow auxiliary information to be stored in function pointers
The MfTXs and mftXd instructions have been renamed to FmvXs and fmvXd
respectively. Similarly, MXTFS and MXTF D instructions have been renamed to FMVsX
and FMVDX, respectivel
The MFFSR and mTFsR instructions have been renamed to FRCsR and Fscsr, respec-
tively FRRM, FSRM, FRFLAGS, and FSFLAgS instructions have been added to individu-
ally access the rounding mode and exception flags subfields of the fcsr
The FMV.. s and FMv..D instructions now source their operands from rs 1, instead of rs2.
This change simplifies datapath design
FCLASSS and FCLasS. D foating-point classify instructions have been added
a simpler nan generation and propagation scheme has been adopted
For RV321, the system performance counters have been extended to 61-bits wide, with separate
read access to the upper and lower 32 bits
Canonical nop and mv encodings have been defined
Standard instruction-length encodings have been defined for 48-bit, 64-bit, and>64-bit in-
structions
Description of a 128-bit address space variant, R.V128, has been added
o Major opcodes in the 32-bit base instruction format have been allocated for user-defined
custom extensions
Volume I: RISC-V Unprivileged IsA v20190608-Base-Ratified
a typographical error that suggested that stores source their data from rd has been corrected
to refer to rs2
Contents
Preface
1 Introduction
1.1 RISC-V Hardware Platform Terminology
1.2 RISC-V Software Execution Environments and harts
1.3 RISC-V ISA Overview
12346
1.4 Memory
1.5 Base Instruction-Length Encoding
7
1.6 Exceptions, Traps, and Interrupts
10
2 RV32I Base Integer Instruction Set, Version 2.1
13
2.1 Programmers' Model for Base Integer ISA
13
2 Base instruction formats
16
2.3 Immediate Encoding Variants
..17
Integer Computational Instructions
2.5 Control transfer lnstructions
21
2.6 Load and store Instructions
24
2.7 Memory Ordering Instructions
.27
2.8 Environment Call and Breakpoints
2.9 HINt Instructions
3“啁 lifencei” Instruction- Fetch fence, Version2.0
31
Volume I: RISC-V Unprivileged IsA v20190608-Base-Ratified
4 RV32E Base Integer Instruction Set, Version 1.9
33
4.1 RV32 Programmers'Model
4.2 RV32E Instruction Set
33
5 RV64I Base Integer Instruction Set, Version 2.1
35
5. 1 Register State
35
5.2 Integer Computational Instructions
35
5.3 Load and store instructions
37
5.4 Hint Instructions
6 RV128I Base Integer Instruction Set. Version 1.7
41
7 M Standard Extension for Integer Multiplication and Division, Version 2.0 43
7.1 Multiplication Operations
43
7.2 Division Operations
44
8
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