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Contents
2.3.29 Serial wire JTAG debug port(SWJ-DP)
2.3.30 Embedded trace Macrocell
Pinouts and pin descriptions
■■■■■■■■■■■
24
4
Memory mapping
38
Electrical characteristics
39
5.1 Parameter conditions
39
5.1.1 Minimum and maximum values
5.1.2 Typical values
5.1.3 Typical curves......,,,,.....
重重
39
5.1. 4 Loading capacitor
39
nput voltage
39
5.1.6 Power supply scheme
40
5.1.7 Current consumption measurement
5.2 Absolute maximum ratings
41
5.3 Operating conditions
42
5.3.1 General operating conditions
42
5.3.2 Operating conditions at power-up/power-down
5.3. 3 Embedded reset and power control block characteristics
5.3.4 Embedded reference volta
44
5.3.5 Supply current characteristics..........
,,,,44
5.3.6 External clock source characteristics
53
5.3.7 Internal clock source characteristics
57
5.3.8 PLL characteristics
58
5.3.9 Memory characteristics
5.3.10 FSMc characteristics
59
5.3.11 EMC characteristics
.,78
5.3.12 Absolute maximum ratings ( electrical sensitivity
79
5.3.13 0 port characteristics
80
5.3.14 NRST pin characteristics
5.3.15 TIM timer characteristics
84
5.3.16 Communications interfaces
85
5.3. 17 CAN (controller area network)interface
,,,,94
5.3.18 12-bit adc characteristics
,95
5.3. 19 DAC electrical specifications
,,,,,,100
Contents
STM32F103XC. STM32F103XD. STM32F103XE
5.3.20 Temperature sensor characteristics
101
6
Package characteristics
102
6.1 Package mechanical data
102
6.2 Thermal characteristics
110
6.2.1 Reference document
6.2.2 Selecting the product temperature range
11
Part numbering
n113
Revision histor
114
4/118
STM32F103xC, STM32F103XD. STM32F103XE
List of tables
List of tables
Table 1
Device summary
Table 2. STM32F103X C, sTM32F103XD and sTM32F103XE features and peripheral counts.. 11
Table 3
STM32F103xX family
12
Table 4. Timer feature comparison
.17
Table 5. High-density STM32F103XX pin definitions
Table 6. FSMC pin definition
Table 7
Voltage characteristics
Table8. Current characteristics
Table 9. Thermal characteristics
42
Table 10. General operating conditions
Table 11. Operating conditions at power-up/ power-down,
42
43
Table 12. Embedded reset and power control block characteristics
Table 13. Embedded internal reference voltage
44
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash
重D
45
Table 15. Maximum current consumption in Run mode, code with data processing
running from rAm
.45
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM
Table 17. Typical and maximum current consumptions in Stop and standby modes
48
Table 18. Typical current consumption in Run mode, code with data processing
running from Flash
..50
Table 19. Typical current consumption in Sleep mode, code with data processing
code running from Flash or RAM
5
Table 20. Peripheral current consumption
··
52
Table 21. High-speed external user clock characteristics
53
Table 22. Low-speed external user clock characteristics
54
Table 23. HSE 4-16 MHz oscillator characteristics
55
Table 24. LSE oscillator characteristics(LSE =32.768 kHz)
Table 25. Hsi oscillator characteristics
57
Table 26, LSi oscillator characteristics
Table 27. Low-power mode wakeup timings
58
Table 28. pll characteristics
58
Table 29. Flash memory characteristics
59
Table 30. Flash memory endurance and data retention
59
Table 31. Asynchronous non-multiplexed sra/PSrAM/NoR read timings
60
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
6
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
62
Table 34. Asynchronous multiplexed PSRAM/NOR Write timings
Table 35. Synchronous multiplexed NOR/PSRAM read timings
..65
Table 36. Synchronous multiplexed PSRAM write timings
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
■
68
Table 38. Synchronous non-multiplexed PSRAM write timings
69
Table 39. Switching characteristics for PC card/CF read and write cycles
,,,,,,,,74
Table 40. Switching characteristics for NAND Flash read and write cycles
Table 41. EMs characteristics
78
Table 42. emi characteristics
79
Table 43. ESd absolute maximum ratings
79
Table 44. Electrical sensitivities
..,79
5/118
List of tables
STM32F103XC, STM32F103XD. STM32F103xE
Table 45. l/o static characteristics
80
Table 46. Output voltage characteristics
Table 47. 0 Ac characteristics
82
Table 48. NRST pin characteristics
,,,,,,,83
Table 49. TIMx characteristics
翻11
84
Table 50. 2C characteristi
85
Table 51. SCL frequency(fpCLK1= 36 MHZ. VDD=3.3 V)
86
Table 52. SPi characteristics
Table 53. 2s characteristics
90
Table 54. SD/MMC characteristics
..93
Table 55. USB startup time.
93
Table 56
USB DC electrical characteristics..……
4
Table 57. USB: full-speed electrical characteristics
94
Table 58. ADC characteristics
95
Table 59. RAIN max for fADC 14 MHZ
....96
Table 60. ADC accuracy-limited test conditions
翻重着■
96
Table 61. ADC accuracy
.....97
Table 62 dac characteristics
100
Table 63. Ts characteristics
101
Table 64. LFBGA144-144-ball low profile fine pitch ball grid array, 10 X 10 mm
0.8 mm pitch, package data
103
Table 65. LFBGA100-low profile fine pitch ball grid array package mechanical data
104
Table 66. WLCSP, 64-ball 4.466 x 4. 395 mm, 0.500 mm pitch, wafer-level chip-scale
package mechanical data
.105
Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data.... 107
Table 68. LQPF100- 100-pin low-profile quad flat package mechanical data
108
Table 69. LQFP64-64 pin low-profile quad flat package mechanical data
109
Table 70. Package thermal characteristics
110
Table 71. Ordering information scheme
113
6/118
STM32F103xC, STM32F103XD. STM32F103XE
List of figures
List of figures
Figure 1. STM32F103XC, STM32F103XD and sTM32F103 E performance line block diagram 22
Figure 2. Clock tree
Figure 3. STM32F103XC, STM32F103XD and STM32F103XE performance line BGA144 ballout. 24
Figure 4. STM32F103XC, STM32F103XD and STM32F103XE performance line BGA100 ballout. 25
Figure 5. STM32F103XC, STM32F103XD and STM32F103xE performance line LQFP144 pinout. 26
Figure 6. STM32F103X C, sTM32F103XD and sTM32F103XE performance line LQFP100 pinout. 27
Figure 7. STM32F103XC, STM32F103XD and STM32F103xE performance line LQFP64 pinout. 28
Figure 8. STM32F103XC, STM32F103XD and sTM32F103XE performance line
WLCSP64 ballout, ball side
29
igure 9
Memory map
38
igure 10. Pin loading conditions
39
Figure 11. Pin input voltage
39
Figure 12. Power supply scheme
40
Figure 13. Current consumption measurement scheme
...40
Figure 14. Typical current consumption in Run mode versus frequency(at 3.6 v)
code with data processing running from RAM, peripherals enabled
,46
Figure 15. Typical current consumption in Run mode versus frequency(at 3.6v)
code with data processing running from RAM, peripherals disabled
46
Figure 16. Typical current consumption in Stop mode with regulator in run mode versus
temperature at different Vop values
Figure 17. ypical current consumption in Stop mode with regulator in low-power
48
mode versus temperature at different Vpp values
Figure 18. Typical current consumption in Standby mode versus temperature at
different Vop values
49
Figure 19. High-speed external clock source AC timing diagram
4
Figure 20. Low-speed external clock source Ac timing diagram
55
Figure 21. Typical application with a 8-MHz crystal
.....56
Figure 22. Typical application with a 32.768 kHz crystal
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
.,60
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms
62
Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms
63
Figure 27. Synchronous multiplexed NOR/PSRAM read timings
64
Figure 28. Synchronous multiplexed PSRAM write timings
66
Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings
68
Figure 30. Synchronous non-multiplexed PSRAM write timings
69
Figure 31. PC Card/CompactFlash controller waveforms for common memory read access
.70
Figure 32. Pc card/compactflash controller waveforms for common memory write access
71
Figure 33. PC Card/Compact hlash controller waveforms for attribute memory read
access
72
Figure 34. PC Card/ CompactFlash controller waveforms for attribute memory write
access
Figure 35. PC Card/ CompactFlash controller waveforms for i/o space read access
73
igure 36. PC Card/CompactFlash controller waveforms for 1O space write access
...74
Figure 37. NAND controller waveforms for read access
76
Figure 38. NANd controller waveforms for write access
,,,,,,,,,76
Figure 39. NANd controller waveforms for common memory read access
,,,,,76
Figure 40. NANd controller waveforms for common memory write access
,,,77
7/118
List of fiqures
STM32F103XC. STM32F103XD, STM32F103xE
Figure 41. 10 AC characteristics definition
83
Figure 42. Recommended NrsT pin protection
84
Figure 43. I]C bus AC waveforms and measurement circuit
86
igure 44. SPI timing diagram- slave mode and CPHA=0
,.,,,,88
Figure 45. SPI timing diagram-slave mode and CPHA=1(1)
...88
89
47. 1s slave timing diagram(Philips protocol 1)
Figure 48. 12s master timing diagram(Philips protocol) (1)
Figure 49. SDIO high-speed mode
Figure 50. s default mode
92
Figure 51. USB timings: definition of data signal rise and fall time
94
Figure 52. adc accuracy characteristi
Figure 53. Typical connection diagram using the ADC
8
Figure 54. Power supply and reference decoupling(VREF+ not connected to VDDA
98
Figure 55. Power supply and reference decoupling (VREF+ connected to VDI
Figure 56. Recommended PCB design rules(0.80/0.75 mm pitch BGA), OA)
Figure 57. LFBGA144-144-ball low profile fine pitch ball grid array 10 x 1D midr
,,.102
0. 8 mm pitch, package outline
..103
Figure 58. LFBGA100-low profile fine pitch ball grid array package outline
104
Figure 59. WLCSP, 64-ball 4.466.395 mm, 0.500 mm pitch, wafer-level chip-scale
package outline
105
Figure 60. Recommended PCB design rules(0.5 mm pitch BGA)
106
Figure 61. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline
Figure 62. Recommended footprint(1)
,,,,,,,,,107
Figure 63. LQFP100, 100-pin low-profile quad flat package outline
.108
Figure 64. Recommended footprint (1)
108
Figure 65. LQFP64-64 pin low-profile quad flat package outline
109
FIgure 66. Recommended footprint(1)
109
Figure 67. LQFP100 PD max vs TA
112
8/118
STM32F103xC, STM32F103XD. STM32F103XE
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103X C, STM32F103XD and sTM32F103XE high-density performance line
microcontrollers. For more details on the whole stmicroelectronics stm32F103xx famil
please refer to Section 2. 2: Full compatibility throughout the family
The high-density STM32F103xX datasheet should be read in conjunction with the
STM32F10xXX reference manual
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10XXX Flash programming manual.
The reference and Flash programming manuals are both available from the
StmicroElecTronicswebsitewww.st.com
For information on the Cortex TM-M3 core please refer to the Cortex TM-M3 Technical
ReferenceManual,availablefromthewww.arm.comwebsiteatthefollowingaddress
http://infocenter.arm.com/help/indexjsp?topic=/com.armdocddi0337e/
Cortex
Intelligent processors by ARM: ARM
9/118
Description
STM32F103xC. STM32F103xD, STM32F103xE
Description
The STM32F103XC, STM32F103XD and STM32F103XE performance line family
incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a
72 MHz frequency, high-speed embedded memories( Flash memory up to 512 Kbytes and
SRAM up to 64 Kbytes), and an extensive range of enhanced l /Os and peripherals
connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16
bit timers plus two PWM timer, as well as standard and advanced communication interfaces
up to two I-Cs, three SPls, two 12Ss, one SDIO, five USARTs, an USB and a Can
The STM32F103xx high-density performance line family operates in the-40 to+105C
temperature range, from a 2.0 to 3.6V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications
The STM32F103xx high-density performance line family offers devices in six different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included the description below gives an overview of the complete range o
peripherals proposed in this family
These features make the sTM32F 103xx high-density performance line microcontroller
family suitable for a wide range of applications
o Motor drive and application control
Medical and handheld equipment
PC peripherals gaming and GPs platforms
e Industrial applications: PLC, inverters, printers, and scanners
e Alarm systems, video intercom, and HVAC
Figure 1 shows the general block diagram of the device family
10/118
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