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详细说明：AD5362_5363AD5362/AD5363
GENERAL DESCRIPTION
The AD5362/ AD5363 contain eight 16-/14-bit DACs in a single
The AD5362/AD5363 have a high speed 4-wire serial interface
52-lead LQFP package or 56-lead I FCSP package. The devices
that is compatible with SPI, QSpt MiCROWIRE", and dsP
provide buffered voltage outputs with a span of 4x the reference
interface standards and can handle clock speeds of up to
voltage. The gain and offset of each DAC can be independently
50 MHz. all the outputs can be updated simultaneously by
trimmed to remove errors. For even greater flexibility, the device
taking the ldac input low. Each channel has a programmable
is divided into two groups of four DACs, and the output range
gain and an offset adjust register.
of each group can be independently adjusted by an offset DAC
Each DAC output is gained and buffered on chip with respect
The AD5362/AD5363 offer guaranteed operation over a wide
to an external siggndx input The dac outputs can also be
supply range with Vss from -165V to-45 V and VDD from 8 V
switched to SIGGNDx via the Clr pin
to 16.5 V. The output amplifier headroom requirement is 1. 4 V,
operating with a load current of l A
Table 1. High Channel Count Bipolar DACs
Model
Resolution(Bits) Nominal Output Span
Output Channels
Linearity Error(LsB)
AD5360
16
4×VREF(20V)
16
AD5361
14
4×VREF(20V)
AD5362
16
4×VR:(20V)
AD5363
14
4×V:(20V)
AD5370
16
4×VREF(12V)
AD5371
14
4×VREF(12V)
AD5372
16
4×VR:(12V)
32
AD5373
14
4×VREF(12V)
32
±1
AD5378
14
±875V
AD5379
14
±875V
Rev. a Page 3 of 28
AD5362/AD5363
SPECIFICATIONS
DVcc=2.5V to 5.5V Vdp=9vto 165V: vss=-165V to-4. V VREF=5V AGND= DGND= SIGGNDO= SIGGNDl=0v
RL=open circuit; gain (M), offset(C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted
Table 2
Parameter
B Version1 Unit
Test Conditions/Comments
ACCURACY
Resolution
16
Bits
AD5362
14
Bits
AD5363
Integral Nonlinearity(INL
±4
LSB max
AD5362
LSB max
AD5363
Differential Nonlinearity(DNL
LSB max
Guaranteed monotonic by design over temperature
Zero-Scale error
±15
my max
Before calibration
Full-Scale error
±20
my max
Before calibration
Gain error
0.1
D FSR
Before calibration
Zero-Scale error
LSB typ
After calibration
Full-Scale error2
LSB typ
After calibration
Span Error of offset DAC
±75
mv max
See the offset dacs section for details
VOUTx Temperature Coefficient
ppm FSR/oC typ Includes linearity, offset, and gain drift
DC Crosstalk
180
μvmax
Typically 20 uV; measured channel at midscale full-scale
change on any other channel
REFERENCE INPUTS(VREFO, VREF1)2
REFx Input current
±10
HA max
Per input; typically +30 nA
VREFx Range2
2/5
Vmin/ max
+2% for specified operation
SIGGNDO AND SIGGND1 NPUTS2
DC Input Impedance
50
ically 55 ko
Input Range
±0.5
Vmin/v max
SIGGNDX Gain
0995/1.005min/max
OUTPUT CHARACTERISTICS2
Output Voltage Range
V5s+1.4
Vmin
1 mA
Vuυ-14
Vmax
lLOAD=1 mA
Nominal output Voltage range
10to+10|V
Short-Circuit Current
15
mA max
VOUTx' to DVcc, VDp, or Vss
Load current
士1
ma max
Capacitive Load
2200
pF max
DC Output Impedance
0.5
Q max
MONITOR PIN(MON OUT)
Output Impedance
DAC Output at positive full scale
1000
&2 typ
DAC Output at Negative Full Scale
500
Q2 typ
Three-State Leakage current
100
na typ
Continuous current limit
ma max
DIGITAL INPUTS
Input High Voltage
17
Vmin
DVcc=2.5V to 3.6V
2.0
Vmin
DVcc=3.6V to 5.5 V
Input Low Voltage
0.8
Vmax
DVcc=2.5Vto 5.5 V
Input Current
HA max
RESET, SYNC, SDI, and sclK pins
a max
CLR, BIN/2S COMP, and GPlO pins
Input Capacitance
10
pF
max
Rev. a Page 4 of 28
AD5362/AD5363
Parameter
B Version Unit
Test Conditions/Comments
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC
Output Low Voltage
0.5
Vmax
Sinking200μA
Output High Voltage(SDO)
D∨-05Vmin
Sourcing200μA
High Impedance Leakage Current
±5
a max
SDO only
High Impedance Output Capacitance 210
pF typ
TEMPERATURE SENSOR(TEMP OUT)
Accuracy
°C
25°C
±5
°Ctyp
40°C
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