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详细说明：FX3_PROGRAMMERS_MANUALContents yCYPRESS EMBEDDED IN TOMORROW 1.1 Chapter Overview 11 1.2 Document Revision History…… 1.3 Documentation Conventions 着1 12 2.1 USB 2.0 System Basics 13 2.1.1 Host, Devices. and hubs 2.1.2 Signaling Rates 11画 2.1.3 Layers of communication flow 13 2.1 4 Device detection and enumeration 18 2.1.5 Power Distribution and Management 19 2.1.6 Device Classes 2.2 USB3.0: Differences and enhancements over USB 2.0 20 2.21.0 Motivation 2.2.2 Protocol Layer 20 2.2.3 Link Layer. 23 2.2.4 Physical Layer. 1面1面面 23 2.2.5 Power Management…… 23 2.3 Reference documents 24 3.1 CPU 26 3.2 Interconnect fabric 27 3.3M 28 3.4 Interrupts 29 3.5 JTAG Debugger Interface 30 3.6 Peripherals 31 3.6.112S 31 3.6.2|2C. 33 3.6.3 UART 34 3.64SP .35 3.6.5 GPIO/Pins… 36 3.6.6 GPIF 41 3.6.7 Storage Interface 42 3.6.8 MIP -CSI2 Interface .43 3.7 DMA Mechanism 44 3.8 Memory Map and Registers 47 3.9 Reset, Booting, and Renum .48 3.10 Clocking 49 3.11 Power 51 3.11.1 Power domains 副面面 51 X3 Programmers Manual, Doc. #001-64707 Rev * K 3 Contents FCYPRESS 3.11.2 Power Management 4.1 System Overview. ∴53 4.2 FX3 Software Development Kit ( SDK) 54 4.3 FX3 Firmware Stack 54 43.1 Firmware framework 54 4.3.2 Firmware API Library 54 4.3.3 FX3 Firmware Examples 55 4. FX3 Host software 4.4.1 Cypress Generic USB3.0 Driver………… 55 4.4.2 Convenience apls 4.4.3 USB Control Center 55 4.4.4 Bulkloop 55 44.5 Streamer……… 56 4.5 FX3 Development Tools 4.5.1 Firmware Development Environment ∴56 4.5.2 GPIF Il Designer 56 5.1 Initialization 57 5.1.1 Device Boot 59 5.1.2 FX3 Memory Organization 59 5.1.3F×3 Memory Map……… 59 5.2 API Libra 64 5.2.1 USB Block 64 5.2.2GP|F‖B|ock 量B面 .68 5.2.3 Serial Interfaces 69 5.2.4 Storage APIs 5.2.5 DMA Engine 72 5.2.6 RTOS and os Primitives .80 5.2.7 Debug Support 81 5.2.8 Power Management 81 5.2.9 LoW Level DMA 81 5.2.10 MIPl-CSI2 Configuration APls 82 7.1 DMA EXamples 85 7.1.1 USBBu| KLoopAuto..….………,………… 85 7.1.2∪ SBBulkLoopAuto Signal… .85 7.1.3 USBBulkLoopManual 85 7.1. 4 USBBulkLoopManuallnout ∴86 71.5 USBBulkLoop AutoOne ToMany…… 8 7.1.6 USBBulkLoopManualOne ToMany 86 7.1.7 USBBulkloop auto Many Tone 86 7.1.8 USBBulkLoopManualMany Toor 71.10 USBBulkLoopManualA,冂e…… 86 7.1. 9 USBBulkLoopMulticast 86 .87 7.1.11 USBBulkLoopManualRem 87 7.1.12 USBBulkLoopLowLevel 87 FX3 Programmers Manual, DoC. #001-64707 Rev. K CYPRES Contents EMBEDDED IN TOMOI 7.1.13 USBBulkLoopManualDCache 87 7.2 Basic EXamples 87 7.2.1 RTOSEXample 87 7.2.2 BulkLpAutoCpp 7.2.3 USBBulkLoopAutoEnum .88 7.2.4 USBBulk Source sink O........ 88 7.2.5 USBIso Source Sink 88 7.2.6 USBlsochLoopAuto 88 7.2.7 USBIsochLoopManuallnOut ∴88 7.2.8 USBBulk Streams 88 7.2.9 USBFlash Prog.… 89 7.2.10 USBCDCDebug 89 7.2.11 USBDebug 89 7.2.12 USBHost 89 7.2.13 USBOtg 90 7.2.14 USBBulkLoopotg 90 7.2.15 Low Powertest 90 7.2.16 GpifTousb 90 7.2.17 USBIso Source 7. 3 Serial Interface Examples 91 7.3.1 GPIO Examples 91 7.3.2 UART Examples 9 7.3.3 12C Exampl 92 7.3.4 SPI Examples 92 7.3.5 12S Examples 92 7. 4 USB Video Class EXample 93 7.4.1 USBVideoclass 93 74.2 USBVideoclass Bulk 93 7.5 Slave FIFO EXamples 93 7.5. 1 Slave Fifoasync 93 7.5.2 Slave FifoAsync5Bit 94 7.5.3 Slave FifoSync 94 7.5.4 Slave FifoSync5Bit 94 7.6 USB Audio Class Example 94 7.6.1 USBAudioClass 94 7.7Cx3 Examples… 94 7.7.1CX3Rgb16AS0260 94 7.7.2Cx3Rgb24AS0260 .94 7.7.3CX3 UVCAS0260. 95 7.74Cx3Uvc○V5640. 95 7.8 Two-Stage Booter(boot fw) Examples 95 7.8.1 Bootledblink 95 7.82FX3 BootAppGcc… 95 7.8.3 BootGpifDemo 95 7.9 Mass Storage Class Example 96 7.9.1 USBMass Storage Demo 7.9.2 FX3SMass Storage 96 7.9.3 FX3SRaido 96 7.10 FX3S Storage Example 96 7.10.1 Gpif To Storage ..a 96 7.10.2 FX3SFile System 96 7.10.3 FX3SSdioUart ∴96 7.11 GPIF-ll Master Example ni0d0000 .97 FX3 Programmers Manual, doc. #001-64707 Rev *K Contents FCYPRESS 7.111 SRAMMaster 97 7.12F×2G2 Example 97 7.12.1 Fx2g2UvcDemo 97 7.13 Co-processor Mode Example 97 7.13.1 Pib slave Demo 97 8.1 Firmware Application Structure…… 99 8.1.1 Initialization code 99 8.1.2 Application Code .103 9. 1 Serial Peripheral (LPP) Registers 113 9.1.112 S Registers………,…,…,…… ∴113 9.1.2 2C Registers 113 9.1.3 UART Registers 114 9.1.4 SPI Registers 115 9.2 FX3 GPIO Register Interface 115 1 Simple GPlO Registers........ 115 9.3 Complex GPIO(PIN) Registers 116 10.1G| ossary… 118 10.2 Externally Visible PP Registers 118 10.3 INTR and dRQ Signaling.. 118 10.4 Transferring Data In and Out of Sockets .119 10.4.1 Bursting and DMA WMARK 11 119 10.4.2 Short transfer-Full Buffer 119 10.4.3 Short Transfer- Partial Buffer 121 10.4.4 Short Transfer- Zero Length Buffers 122 10.4.5 Long Transfer- Integral Number of Buffers 123 10.4.6 Long Transfer- Aborted by AP 124 10.4.7 Long Transfer- Partial Last Buffer on Ingress 12 10.4.8 Long Transfer-Partial Last Buffer on Egress 125 10.4.9 Odd-sized transfers 10.4.10DMA transfer signalING on ADMUX interface 126 11.1 Firmware Image Storage Format …130 12.1 GNU Toolchain 133 12.2 Eclipse Ide 133 13.1 FX3 Host software 135 13.1.1 Cypress Generic Driver.…………. 135 13.1.2 CYAPI Programmer's Reference 135 13.1.3 CYUSB. NET Programmer's Reference 135 13.1.4 Cy Control Center .136 FX3 Programmers Manual, DoC. #001-64707 Rev. K CYPRES Contents EMBEDDED IN TOMOI FX3 Programmers Manual, doc. #001-64707 Rev *K Contents FCYPRESS FX3 Programmers Manual, DoC. #001-64707 Rev. K 1. ntroduction 6ECYPRESS EMBEDDED IN TOMORROW Cypress Ez-USB FX3 TM is the next-generation USB 3.0 peripheral controller providing highl integrated and flexible features that enable developers to add UsB 3.0 functionality to any system Figure 1-1. EZ USB FX3 System Diagram JTAG Debug Probi JIAG Controlle RAM ASIC GPIF II Peripheral EPs Image Sensor PMMC HS/FS 凰 SPI SD/MMCIS □ FX3SDeviceOnly FPGA SDIO Device Sensor eMMC Flash EZ-USB FX3 has a fully configurable, parallel, general programmable interface called GPIF TM Il which can connect to any processor, ASIC, DSP, image sensor, or FPGA. It has an integrated PhY and controller along with a 32-bit microcontroller(ARM926EJ-S)for powerful data processing and for building custom applications. It has an interport DMA architecture that enables data transfers of greater than 400 MBps FX3 is a fully compliant USB 3.0 and USB 2.0 peripheral. An integrated USB 2.0 OTG controller enables applications that need dual role usage scenarios. It has 512 KB of on-chip SRAM for code and data. It supports serial peripherals such as UART, SPl, 12C, and 12S that enable communicating to on board peripherals; for example, the 12c interface is typically connected to an EEPROM GPIF II is an enhanced version of the GPif in FX2LP TM, Cypress's flagship USB 2.0 product. It provides easy and glueless connectivity to popular industry interfaces such as asynchronous and synchronous Slave FIFo, asynchronous SRAM, asynchronous and synchronous Address data Multiplexed interface, parallel ATA, and so on. The gPiF ll controller on the fX3 device supports a total of 256 states. It can be used to implement multiple disjointed state machines The FX3 also supports a Pseudo multiMedia card(PMMC)or MMc slave interface through which it can be connected to processors that support an SD or MMC memory interface. This interface uses the same pins as the GPIF-I and the user has to choose between the GPIF-lI and MMC interfaces X3 Programmers Manual, Doc. #001-64707 Rev * K 9 Introduction CYPRESS EMBEDDED IN TCMORROW The FX2G2 device is a USB 2.0 controller, which supports all other features of the FX3 controller The ARM9 core and DMA capabilities, along with the GPIF-IlI support, make this a high-performance USB 2.0 controller FX3 is fully compliant with USB 3.0 V1.0 Specification and is also backward compatible with USB 2.0. It is also complaint with the Battery Charging Specification V1. 1 and USB 2.0OTG Specification The FX3s device is an extension to the fX3 that supports a storage interface that can be connected to Sd cards or eMMC devices. The FX3s device allows developers to add high performance persistent storage interfaces to their USB design, and supports the SD 3.0 specification and the MMC 4.41 specification The Benicia device is similar to the FX3s device but comes in a smaller wafer-level chip scale package(WLCSP). The Bay device is a USB 2.0 only version of the Benicia controller. The small chip footprint and high-performance flash memory support (SD/eMMC) make these devices a good fit for solutions such as mobile phones The SD3 device is a programmable USB 3.0 to SD/eMMC/SDIo bridge device based on the FX3 architecture. This device does not support the GPIF- or PMMC interfaces The Ez-USB CX3 device is an extension of the EZ-USB FX3 device. It includes the ability to interface with and perform uncompressed video transfers from image sensors implementing the MIPI CSI-2 interface over a fixed -function gpif interface The FX3 comes with the easy-to-use EZ-USB tools providing a complete solution for fast application development. The software development kit includes application examples to accelerate time to marke The FX3 product family has multiple devices with a varied feature set. The FX3 SDK works with all of the FX3 and FX3S parts and is capable of identifying the type of device being used at runtime. Refer to Table 1-1 for details of the features supported by each of the FX3 and FX3S parts Table 1-1. Features Supported by FX3 and FX3S Parts CYUSB3014 Yes Up to 32 bit No 512KB CYUSB3013 Yes Up to 16 bit No 512KB CYUSB3012 Yes Yes Up to 32 bit No 256KB CYUSB3011 Yes Yes Up to 16 bit No 256KB CYUSB3035(FX3S) Yes Yes Up to 16 bit YE es 512KB CYUSB3025 (SD3) Ye es es N Yes 512KB CYUSB2104(FX2G2 Yes Up to 32 bit No 512KB CYUSB3065 (CX3) CS-2 Yes No 512KB interface CYWB0263 Benicia) Yes Up to 16 bit Yes 512KB CYWB0163 (Bay) Yes Up to 16 bit Yes 512KB 10 FX3 Programmers Manual, Doc. #001-64707 Rev *K

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