AN_412_FT600_FT601 USB Bridge chips Integration.pd

文件名称: AN_412_FT600_FT601 USB Bridge chips Integration.pdf

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详细说明：_FT600_FT601 USB Bridge chips IntegrationApplication Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 1 Introduction The FT600 and FT601, collectively referred as FT60x, are designed to bridge UsB packets from USB2.0 and UsB30 hosts to a USB function through a FIFO interface. The bridge implements the FIFo slave interface which may be configured as a FT245(single channel or Ft600(multi-channel) bus. In typica designs an fPga is used to implement the fifo master interface to communicate with the bridge. th FPGA and other devices(not shown)implement the remaining features of the target UsB function(s).The bridge handles all USB related configuration control and data transfer and simplifies customer designs that require an usB2. 0/UsB30 device port FIFO Interface USB20/30 (FT245/FT600) USB Host FT60 FPGA USB Device FIFO Slave FIFO Master Port Interface Interface Figure 1-FT6ox System Block Diagram Product Page Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 2 Data transfer semantics The FT600 and FT601 bridges may be viewed as USB-FIFo translators i.e. any UsB bulk packet from the USB host is placed into a FIFo for the FIFo master to read and any data from the FIFo master is in turn carried as USB bulk packets. In order to achieve a high throughput on the bus the fifo master shall be designed to read or write in maximum sized packets except for the last packet in a transfer. This ensures high efficiency on the USB The length of data to be exchanged between host and function is carried in a session message from the driver to the bridge In the in direction the fifo master has to be designed to write in maximum sized packets except for the last packet which must be a short packet. This ensures that the bus bandwidth is used efficiently. When the FIFO master is designed to write in random sized bursts and when these bursts result in short packets then the transfer requests will be ended prematurely. Figure 2- Read pipe semantics- shows two behaviors controlled via the chip configuration The upper half of the figure shows the default behavior of the bridge in the read direction The application has requested 3072 bytes; however, the FIfo interface master only wrote 1024 bytes and stopped. The bridge detects this as a session underrun and terminates the read session and returns the data collected to the host The lower half of the figure shows the behaviors of the bridge when it is configured to keep the session as long as the maximum sized packets are written into the FIFo. In this configuration the session is not terminated when the master pauses between writing maximum sized packets. The session is ended when the full length of data is received by the bridge(shown or if a short packet is written(not shown). Cancel session API FIFO On Underrun is Enabled TXE Asserts (default) FT ReadPipe returns 1024B Master writes and pauses at with 10248 maximum packet size TXE N negates(master stopped before full length was reached) FT-ReadPipe(3072B),L. Cancel session TXE N asserts On Underrun is 1024B Master writes and Disabled pauses at maximum packet size boundary TXE N remains asserted 1024B Master writes and pauses 2 TXE N remains asserted FT ReadPipe returns 1024B with 30728 Master writes and pauses TXE_N negates Figure 2-Read Pipe Semantics In the out direction the FIFo master has to be designed to read out all the data from the host. If data is not read out promptly then the out path may be bottlenecked and result in a write timeout. There is no nechanism for the FIfo interface master to drop"the data in the write pipe 4 Product Page Document feedback Copyright C Future Technology Devices International Limited FTDI Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 Master shall always read out until RXF N FIFO negates(FIFO is FT_ WritePipe(4 empty FT Write Pipe returns RXF N asserts 4E FT WritePipel Master reads data is transferred FT WritePipet21761 >RXF N negates and to Maaster 1024B master stops 1024B RXF Asserts FT WritePipe returns 128B and pauses 124 FT WritePipe[2176 RXF N remains data is transferred to asserted Master 512B Master reads RXF N negates and Figure 3- Write Pipe Semantics The designer is advised to check chip errata TN 168 FT600 601 Errata Technical Note, so that the appropriate workarounds may be designed to overcome the errata 5 Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 3 Operating Modes 3. 1 Chip Configuration The chip is highly configurable and configurations are intended to provide flexibility in the manner in which USB packets are exchanged between the host and usb function(FIfo master. the important configuration options are explained below 1. fifo bus interface selection 2. FIFo channe and buffer selection 3. Session Underrun Handling 4. Notification Pipes 3.11 FIFO Bus Interface The FIFo interface may operate in FT245 mode or in FT600 mode. The FT245 mode is a popular FTDI proprietary bus interface supported by most FTDi USB2.0 bridge devices. The ft600 mode is also a FTDi proprietary bus implemented in the ft600 and ft601 devices The main difference between FT245 and FT600 bus interfaces is the number of channels that they are able to support. The FT245 bus interface does not carry channel information and therefore supports only one channel while the FT600 bus interface is defined for up to 4 channels. Each channel is bi-directional 3.1.2 FiFo Channel and Buffer There are internal buffers in the device that are sized automatically depending on the number of channels that are configured. Each channel has 2 buffers(ping-pong)in each direction Bus Interface Channel Direction Buffer size in each direction FT245 IN only (uni-directionad) 8KB OUT only(uni-directional) 8KB in out 4KB FT600 IN only(uni-directional) 8KB ouT only(uni-directional 8KB in out 4KB in out 2KB Not supported in out 1KB Table 1- fifo channel and Buffer 6 Product Page Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 3.1.3 Session Underrun Handling A session is initiated when a transfer request is initiated by the user application a call to ft ReadPipe or FT_Write Pipe initiates a session. A session may trigger one or more transfer requests at the UsB transfer level. the FIFo master reads or writes to the fifo only when it is signaled that space or data is available for writing or reading A session underrun is a condition that occurs on IN endpoints. a session underrun is detected when the master stops writing(FT245 mode: WR_N is negated before TXE_N is negated)while there is more space in the FIfo to accept data. When this condition is detected, the data in the FIfo is transferred to the host The device may be configured to disable underrun detection see the F[60X Configuration Programmer User guide for further information When detection is disabled, the session remains open as long as the master pause the write at multiples of maximum sized packets of data and continues until the full length is reached 3.1.4 Notification Pipes Notifications may be enabled and only apply to IN endpoints of a channel. They are provided as a means to signal to the host how much data has been written into the fifo by the master the length of data that can be written is limited by the size of the buffer which is configured according to the number of channels. For example in FT245 mode, the FIfo size is configured as 4KB and in each write, the master may only write 4KB of data In order to receive notifications the user application has to register a callback with the aPI. When a notification is received the call back to the user application indicates the length of data written into the FIFO and the user application must issue an ft read Pipe to read exactly the length of data reported in the callback notification. Reading less data than was signaled in the notification callback may result in ReadPipe timeouts. Consequently the user application shall only issue an ft_Read Pipe when notified and not independently of a notification When notifications are enabled on any endpoint then the device will not be placed into selective suspend by the driver to ensure that the Fifo interface clock is not turned off. 3.1.5 GPIO Configuration Two GPIo pins may be configured for general usage. these pins may be configured as input or output pins. The availability of the pins as GPio is dependent on the chip configuration At power-up or after a reset the bridge checks if a valid chip configuration is present in the non-volatile memory. If a valid chip configuration is found, the pins are treated as user configurable GPio pins otherwise the GPio pins are treated as interface configuration pins and not available for GPIO operation Chip Configuration: valid GPIo[1: 0] Direction Data Interpretation User configurable Input or Output User defined User defined Chip Configuration: Invalid GPo[1:01 Direction Data Interpretation Product Page Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 Not available Input 2b00 FT245 2b01 FT600-1 Channel 2b10 FT600-2 Channel 2b11 FT600-4 Channel Table 2- GPIo Configuration When the GPio pins are available for general usage, they may be configured via the chip configuration and, additionally, via the GPIo APi at run-time. The driver reads the chip configuration to determine the default state of the gPio pins and keeps track of the changes to GPIo settings and directions. However, in cases where the driver is re-loaded without the bridge being reset in tandem (e.g. in self-powered devices, there is a chance that the le drivers status and the actual pin status become unsynchronized. In this case, the application has to ensure that the gpio direction and settings are synchronized When the chip configuration has been erased or is invalid the user application may not use the gPio pins and shall not use the gPIo apis 3.2 Abort Recovery Sometimes a user application may wish to restart and reinitialize communication with its FIFo master. At other times, the FIFo master may become unresponsive or the bridge itself may enter into an unresponsive state. When the bridge or FIFo master is unresponsive, the application detects this via two requirements to be fulfilled from the application leve to recover from such an exception, there are 1. The application has to signal to the fifo master that an abort is in progress. this signaling has to be carried out in an Out-Of-Band(oob) manner. 2. The FIFo master needs to perform an unaligned write on the in fifo and a continuous read on the out fifo in order to clear the fifos When FT_ AbortPipe is called on a pipe, it causes all data that buffered in the pipe to be removed. The pipe is a logical construct that has one end at the d3XX APi and the other end at the FIFo interface. The following sections illustrate read and write pipe abort recovery procedures API FIF FT ReadPipell XE N asserts Master writes and FT ReadPipe stops returns with Timeout error TXE N remains asserted DOB Enable Signal Ta FIFO Master Master performs an aligned write 10ms timer started TXE_N is negated FT_Abort( Return from K Pipe is empty FT AbadtPipe OOB Disable Signal To FIFO Master Figure 4- Read Pipe abort Recovery Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 The read pipe abort recovery process is as follows 1. FT ReadPipe is called on a pipe 2. FT_Read Pipe returns with a timeout error. 3. Application initiates abort recovery 4. Application asserts a read side oob signal to the FIFO master 5. FIFo master detects the read side oob signal assertion 6. FIFo master performs an unaligned write if the corresponding fifo data signal is asserted (e. g. in FT245 mode, the TXE_N signal is asserted low when the FiFo has space to receive data. An unaligned write ensures that the corresponding session at the bridge is closed and tXe_n will be negated 7. Application waits 10ms (or longer depending on FIFO master design) 8. Application calls FT abortPipe and returns 9. Application negates the read side oob signal to the fifo master 10. abort procedure ends (pipe is empty) 11. Application may resume data transfer FIFO FT_ WritePipe( RXF N asserts Master reads and FT Write Pipe returns with timeout error REmains asser OOB Enable Signal To FIFO Master Master rea ds continuously until RXF N negates 10m5 timer started FT AbortPipe( RXF Nis negated == Timer must ensure that PIpe is empty master has sufficient time Return from to read all data out from FT AbortPipe the pipe 0oB Disable SignalTo FIFO Master Figure 5 -Write Pipe abort Recovery The write pipe abort recovery process is as follows 1. Ft WritePipe is called on a pipe 2. FT WritePipe returns with a timeout error. 3. Application initiates abort recovery 4. Application asserts a write side OOB signal to the FIFo master 5. Application starts a 10ms(or longer) delay timer 9 Product Page Document feedback Copyright C Future Technology Devices International Limited Application Note Chip AN_412 FT600-FT601 USB Bridge chips Integration Version 1.1 Document reference no,: ft 001332 Clearance no: FtDi# 505 6. FIFO master detects the write side OoB signal assertion 7. FIFO master reads data from the pipe until no more data is signaled (e.g. In FT245 mode, rXe_n ignal is negated) 8. Application timer expires 9. Application calls ft abortPipe and returns from the call 10. Application negates the write side oOb signal to the FIFo master 11. abort procedure ends(pipe is empty) 3.3 ooB Signals 3.3.1 GPIO as ooB Signals The bridge provides 2 user programmable GPIo signals that may be used in a variety of ways 1. The two GPIo signals may each be used as a read side oob and a write side ooB signal. This allocation works well with the ft245 bus interface mode 2. If a FIFo master reset is required then one gPio signal may be used as a FIfo master reset signal and the other as the oob signal. In this situation the oob is treated as a global oob for all channels 3.3.2 Channel status as ooB signals In the FT600 interface mode up to 4 channels may be used. then if there are any unused channels, the status bits of unused channels may be used to signal an oob to the FIFo master. However, allocating an unused channel reduces the fifo buffer allocated to the other channels. So, the designer has to balance FIFo buffer size and application bandwidth requirements against flexibility of using the status bits as OOB signals For example if only two channels are used in FT600 mode then the status bits of the other two channels may be used to signal OOB. A read or write on the unused pipe may be used as a signal to the FIFo master that an abort is required in the corresponding direction the fifo interface master has to remov the data in the out endpoint or write data into the in endpoint to acknowledge" the oob request 10 Product Page Document feedback Copyright C Future Technology Devices International Limited

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