DS_UMFT60xx module datasheet.pdfUMFT60xx module da

文件名称: DS_UMFT60xx module datasheet.pdf

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详细说明：UMFT60xx module datasheetFTDI UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 Table of contents 1 Ordering Information 1 2 Hardware Description 3 2.1 Physical Description asa. 5 2.1.1 Dimensions 2.2 Connectors, Jumpers and push Buttons ■■■■■■■■■■■■■■■■■■■■■■■ 2.2.1 CN1-Micro USB30 Receptacle 2.2.2 CN2- POWER JACK 2,1MM 2.2.3 JP1-External/VBUS 2.2.4 JP2-VCC33 Selection 2.2.5 JP3 JP6-VCCIO Selection.....,... 2.2.6 JP4, JP5-FIFO mode selection and GPIo pin out 2.2.7 SW1, SW2- Push Buttons for Reset and remote Wake Up 2.2.8 CN4 - FMC/ HSMC FIFO bus interface connector 3 Board schematics…n n13 4 Hardware Setup Guide…………… a18 4.1 Power Configuration mB.BOIABIORIBIIIBIAIIIIaIIIn. 18 4.2 Jumpers Default Position………………………………………18 4.3 Power Consumption…… 19 5 Contact information ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 20 Appendix A- References 21 Document Acronyms and Abbreviations. ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 21 Appendix B- List of tables& k Figures…… 22 List of tables n22 st of Figures…………… 22 Appendix C- Revision History…………………………23 Copyright Future Technology Devices International Limited 2 FTDI UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 2 Hardware Description uMFT600A16012015 }3x ee且 Figure 2-1 UMFT600A Module Top and Bottom view UMFT601A16012015 Nw432稀Y10 图话骚 Figure 2-2 UMFT601A Module Top and Bottom view FTDI UMFT600 mie10262/14 排: 哥 H →9 Figure 2-3 UMFT600X Module Top and Bottom View Copyright Future Technology Devices International Limited UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 43 HV10 UMFTE0IX 2672/01 →9月 Figure 2-4 UMFT601X Module Top and Bottom View The main functions of the umft6oxx module are as follows Provides multi-channel FIFo mode and 245 Synchronous FIFo mode protocols, configured by GPIOs Configurable FIFo clock: 66.67MHz and 100MHz(100MHz only for 2. 5v or 3. 3V VCCIO) default clock is 100mhz High speed FIFo bus interface: FMC(Low Pin Count) and HSMC optional. See Ordering Information Jumpers selection allowing powered options: VBUS-powered, External DC-powered, FIFo master board-powered Multi voltage VCCIo option: 1. 8V,2.5V,3.3V. Configurable gPios Hardware reset and remote wake up support Available with 1 6bit and 32 bit wide fifo bus Copyright Future Technology Devices International Limited 4 UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 2.1 Physical Description The UMFT600A/UMFT601A and UMFT600X/UMFT601X modules dimensions are illustrated in Figure 2.5 to Figure 2.8 211 Dimensions 71,12 381 p甲。°3号 UMF601A1003/2015 432RE￥11 60.0 F 7 RP6 RP5 m一 50.485 需号 CN2 C7B605 3.78 78.7 Figure 2-5 UMFT600A/UMFT601A Dimensions(Top view) 11.2 4.5 Figure 2-6 UMFT6OOA/UMFT601A Dimensions(Side view) ±0.10mmTo| erance all dimensions are in mm Copyright Future Technology Devices International Limited 5 FTDI UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 63.56 3.515K科 11.33 FTD° 督日号5昏学骨分9修铲命1 ##-EH1ipa HW 4Z1RFV L UMF 1600X 003/2015 60.0 啊啊已已心凵 70.0 Figure 2-7 UMFT600X/UMFT601X Dimensions(Top view) 11.2 1.6 6.3 Figure 2-8 UMFT60OX/UMFT601X Dimensions (Side view) 士0.10 mm tolerance all dimensions are in mm Copyright Future Technology Devices International Limited 6 UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 2.2 Connectors Jumpers and push Buttons Connectors, jumpers and push buttons are described in the following sections 2.2.1 CN1- Micro USB3 0 Receptacle Pin no Name Type Description VBUS P 5V DC power supply 2 IO SB D-line D+ USBD+line 4 5 GND P Ground 6 SSTX- Super Speed USB transmitter differential pair (-) SSTX+ Super Speed USB transmitter differential pair (+) 8 GND P Ground SSRX Super speed USB receiver differential pair(-) 10 SSR+ I Super Speed USB re ferential pair (+) Table 2.1 cn1- micro usb,0 pin-out 222 CN2- POWER JACK 2 1MM Optional external dC 5v input. Pin no. Name Type Description 1 5V P 5v power supply 2 GND P Ground Ground Table 22 cn2- power jack 2 1MM 2.2.3 JP1 -External/vBus powered selection Select whether the module power is supplied by an external dc 5v or VBUs. Note this setting must be chosen in conjunction with the JP2 setting Default is open: LNoteJ Jumper position Description Short pin 1-2 Select VbUs Power Short pin 2 Select external Dv 5v Table 2.3 JP1-5v input Options Copyright Future Technology Devices International Limited UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 2.2.4 JP2-vcC33 Selection Select whether the module main power is supplied by dc5v or the FIFo master board DC33V INote! Jumper position Description Short pin 1-2 Select powered by external DV5V or VBUS Short pin 2-3 Select powered by FIFO master Board(default) Table 2.4 JP3-VCc33 option 2.2.5 ]P3 JP6- VCCIO Selection Select the io voltage level.[Ncte Jumper position Description JP3 JP6 Short pin 1-2 Open VCCIo=2.5v(default) Short pin 2-3 Ope en VCCIO=1.8V Open Short VCCIO=3,3V Table 2.5 JP3-VCcIo Option 2.2.6 JP4, JP5-FIFO mode selection and GPIo pin out Select Multi-channel FIFO mode or 245 Synchronous FIFo mode JP4 pin2 is GPIo_0 pin out and JP5 pin2 is GPio_1 pin out Jumper position GPIO valid Channel FIFO Mode GPIo 1 JP4 JP5 NO GPIO 0 JP4 pin2) OP5 pin2) 1-2(or open) 1-2(or open) Mu|tⅰ- Channe|FIFO Yes Yes 1-2(or open) 2-3 Mu|tⅰ- hanne|FIFo 2 Yes No 2-3 1-2(or open Mu|tⅰ- Channe|FIFo 1 No Yes 2-3 2-3 245 Synchronous FIFo 1 NO No Table 2. JP4, JP5-Configurations Note: Please refer to section 4 Hardware setup guide for more details power configuration options and jumpers positions. 2.2.7 SW1, SW2 -Push Buttons for Reset and Remote Wake Up SW1 -Reset, module hardware reset mapped to FMC/ HSMc connector, can be used for FIFo master reset Drive low when press down. Copyright Future Technology Devices International Limited 8 UMFT6OX FIFO To USB 3.0 Bridge Evaluation Board Version 11 Chip Document Reference no. ft 001191 Clearance No. FTDi#457 SW2- Remote Wake Up drive low when press down 2.2.8 CN4-FMC/ HSMC FIFo bus interface connector 2.2.8.1 FMc connector configurations-UMFT60OX/UMFT601X Module UMFT600X UMFT601X FMC Pin#/Name U1: FT600 Pin#/Name U1: FT601 Pin=f/Name C14/LA10 P 11 /Wake up_N(Optional, default: OPEN)[ 16/Wake up_N(Optional, default: OPEN) C15/LA10 N 10/RESET N 15/RESET_N C18/ LA14 P 12/GPIO_O(Optional, default: OPEN) 17/GPIO_0(Optional, default: OPEN) C19/LA14N 13/ GPIO_1(Optional, default: OPEN) 8 /GPIO_1(Optional, default: OPEN) C22/LA18 P CC 43/D_CLK(FIFO bus clock, FT600 output) 68/D_CLK(FIFO bus clock, FT601 output) C26/LA27 P N. C 62/DATA18 C27 LA27 N N. C 60/DATA16 D14/LA09 P N C 8/BE N 3 D15/LA09 N N. C 7/BE N 2 D20/LA17P CC N. C 76/DATA31 D21/LA17 N CC N C 75/ DATA30 D23 /LA23 P N. C 70/DATA25 D24/LA23_N N 69/DATA24 D26/LA26 P 63/DATA19 D27/LA26_N N. C 61/DATA17 G6/LA00 P CC N. C 13/OE_N G7/LAOO N CC N c 12/RD N G12/LA08 P N C 11/ WR_ N G13/LA08 N N. C 10/SIWU_ N G21/LA20 P 9/OE_N 74/DATA29 G22/LA20_N 8/RD N 73/DATA28 G24/ LA22P 7/WR_N 67/ DATA23 G25/LA22N 6/ SIWU N 65/DATA21 G27/LA25 P 56/ DATA15 57/DATA15 G28/LA25 N 54/DATA13 55/DATA13 Copyright Future Technology Devices International Limited

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