ft601-DATASHEETFT601-DATASHEETFT600Q-FT601Q IC Dat

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详细说明：FT601-DATASHEETFT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document no∴:F001118 Clearance No: FTDiT424 2 Block Diagram FIFO FIFO BUS PROTOCOL MANAGEMENT NVM GPIO LDO USB3.0 CONTROLLER WAKE UP POWER VCC33 MANAGEMENTH-VCCIO PIPE-IF UTMI-H PLL CLOCK 3OMHZ CRYSTAL RESET BCD uSB3,0 PHY uSB2.0 PHY 5Gbps 80Mbps/12Mbps Figure 2.1 Block Diagram Notes: FT600Q(QFN-56 has a 16-bit FIFo bus interface and Ft601Q(QFN-76 has a 32-bit FIFo bus terface For a description of each function please refer to Section 4 Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document No. F 001118 Clearance No: FTDiT424 Table of contents 1 Typical Applications.. 11 Driver Support…… 12 Ordering Information…… ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 1.3 USB Compliant 22223 2 Block Diagram ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■國 3 Device Pin Out and signal Description…………6 3.1 Device pin out ■■■■■■■■■■■■■■ 6 32 Device Pin Out Signal Description…… ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 7 4 Function Description 11 4.1 Key Features and Function Description…………………………………11 42 Multi-channel fifo mode protocols n13 4.3 245 Synchronous FIFo mode protocols mmmamaaIa 16 4.4 FIFO Bus AC Timing………18 4.5 Crystal requirements…… ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 18 5 Devices Characteristics and Ratings……………19 5.1 Absolute Maximum Ratings…… n19 5.2 ESD and Latch- up Specifications……………………………………………19 5.3 DC Characteristics 5.3.1 DC Characteristics (Ambient Temperature =-40C to+85C).....,....... 20 5.3.2 DC Characteristics for I/o Interface 21 6 USB Power Configurations…………22 61 USB Bus- Powered Configuration………………………………22 62Self- Powered Configuration…………………………… 23 7 Application Example ■■■■■■■■■■■■■ ■■■■■■■■■■■■■■■■■■■l ■■■ 24 7.1FT600/FT601 Connect to FIFO Master Interface………24 8 Package Parameters 25 81QFN-56 Package Mechanical Dimensions∴………………25 8.2 QFN-56 Package Markings 26 8.3 QFN-76 Package Mechanical Dimensions 27 84QFN-76 Package Markings………………………………………………………,……28 8. 5 Solder reflow profile ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 29 Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 〔hip Document No. F 001118 Clearance No: FTDiT424 9 Contact information Appendix a- References∴… n31 Document References n31 Acronyms and abbreviations,……31 Appendix b- List of Figures and tables…………… 32 List of Figures n32 List of tables uuumuwuuwu 32 Appendix c- Revision History………………… 33 Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document no∴:F001118 Clearance No: FTDiT424 3 Device Pin Out and signal Description 3.1 Device pin out 59> AVDD1 42 DATA 7 BE 02 41 DATA 6 BE 13 40 DALA 5 FTDI (39DAIA 4 RXF N5 CIO SIWU N6 (37 VD1U WR N XXXXXXXXXX (36 DATA_3 RD 35 DATA 2 OE N9 FT600Q G4DATA_1 RESET N1O 33 DATA 0 WAKEUP N GPIOO 12 YYWW-B 32GND 1Dv10 GPIO1 13 VCC33 RESERVEl4 2臭云目> c Figure 3.1 QFN56 Package Pin Out Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document No. F 001118 Clearance No: FTDiT424 (7DATA 15 AVID DATa 14 VD10|3) DATA 13 BEat BE 15 SFTDI DATA 12 的DATA11 B2|6 52DATA 10 BE 3 1DATA 9 XXXXXXXXXX SolDATA 8 RXE N9 VCCIO SIWU N1O) 48VD10 WR Nu1) 47 DATA 7 RD NI2 FT601Q DATA 6 OE N DATA 5 ⅤCCI4 DATA 4 RESET N15 WAKEUP N1o YYWW-B 43DATA 3 42 DATA 2 DATA 1 GPIo山18) DATA O RESERVE19 9 DV10 9到自自 Figure 3.2 QFN76 Package Pin Out 3.2 Device Pin Out signal Description Pin No Pin Name Description Type QFN76QFN56 Parallel FiFo bus clock output pin to FIFo bus master, the Frequency can be configured as 66Mhz or 100Mhz for both FIFO O CLK bus modes 58 43 DATA O Parallel FiFo bus data i o bit 0 I/O 40 33 DATA 1 Parallel Fifo bus data i o bit 1 /O 41 DATA 2 Parallel FIFo bus data I/o bit 2 I/O 2 35 DaTa 3 Parallel FiFo bus data i/o bit 3 I/O 43 36 DATA 4 Parallel FIFo bus data I/o bit 4 I/O 44 39 DATA 5 Parallel Fifo bus data I/o bit 5 I/O 45 40 DATA 6 Parallel Fifo bus data i o bit 6 I/O 46 41 DATA Z Parallel FiFo bus data i o bit 7 I/O 47 42 daTa 8 Parallel FIfo bus data i/o bit 8 I/O 50 45 Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document no∴:F001118 Clearance No: FTDiT424 daTa 9 Parallel FIFo bus data i/o bit 9 I/O 51 46 DATA 10 Parallel FIFo bus data i/o bit 10. I/O 52 47 DATA 11 Parallel FIFo bus data I/o bit 11 I/O 53 48 DATA 12 Parallel fifo bus data i/o bit 12 I/O 54 53 DATA 13 Parallel FiFo bus data i o bit 13 I/O 55 54 DATA 14 Parallel FIFo bus data i/o bit 14. 56 5 DATA 15 Parallel FIFo bus data i/o bit 15. I/O DATA 16 Parallel FIFo bus data i/o bit 16. I/O 60 N/A DATA 17 Parallel FIFo bus data I/o bit 17. I/O 61 N/A DATA 18 Parallel FIFo bus data I/o bit 18 yO 62 N/A DATA 19 Parallel FiFo bus data I/o bit 19 I/O 63 N/A DATA 20 Parallel FiFo bus data i/o bit 20 I/O 64 N/A DATA 21 Parallel FIfo bus data i/o bit 21. I/O 65 N/A DATA 22 Parallel FIFo bus data i/o bit 22 I/O 66 N/A DATA 23 Parallel FIFo bus data i/o bit 23. I/O 67 N/A DATA 24 Parallel FIFo bus data I/o bit 24. I/O 69 N/A DATA 25 Parallel FIfo bus data I/o bit 25 I/O 70 N/A DATA 26 Parallel FiFo bus data i/o bit 26 I/O 71 N/A DATA 27 Parallel FIFO bus data i/o bit 27. I/O 72 N/A DATA 28 Parallel FIfo bus data i/o bit 28. I/O 73 N/A DATA 29 Parallel FIFo bus data i/o bit 29. I/O 74 N/A DATA 30 Parallel FIfo bus data i/ o bit 30 I/O 75 N/A DATA 31 Parallel FIFo bus data I/o bit 31 I/O 76 N/A BE O Parallel Fifo bus byte enable i/o bit o I/O 4 Parallel FiFo bus byte enable i/o bit 1 I/O Parallel FIfo bus byte enable I/o bit 2 I/O ′A BE 3 Parallel FIfo bus byte enable I/o bit 3 I/O N/A 245 Synchronous FIFo mode: Transmit FIFo Empty output signal The signal indicates there is a minimum of 1 byte of space available to write to. Only write to the FIFo when this signal is gIC TXE N Multi-Channel FIFo mode: Status Valid output signal (optional) Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document no∴:F001118 Clearance No: FTDiT424 245 Synchronous FIFo mode: Receive FIFO Full output signal The signal indicates there is a minimum of 1 byte of data available to read. Only read from the Fifo when this signal is gIc Multi-Channel fifo mode: Data receive acki ge outpu signal. 9 SIWU N Reserved. Add external pull up in normal operation 10 6 245 Synchronous FIFo mode: Write Enable input signal Multi-Channel FIFO mode: Data Transaction Request input signal WR N The signal is active low 7 245 Synchronous FIFO mode: Read Enable input signal RD N The signal is active low. 12 245 Synchronous FIFO mode: Data Output Enable input signal. OE N The signal is active low. 13 RESET N Chip reset input active low 15 10 Suspend/Remote Wakeup pin by default Low when USB is active high when USB is in suspend. Application can drive this pin low in in USB suspend to generate a remote wakeup signal to the USB WAKEUP N host 16 11 Reserved Do not connect NC 19 14 GPIOO Configurable GPio porto I/O 17 12 GPIO 1 Configurable GPIo port1. I/O 18 13 VBUS USB BUS power input. 37 29 Crystal input. This terminal is the crystal input for the internal XI oscillator 21 16 Crystal Output This terminal is the crystal output for the interna XO oscillator 22 17 DP High-speed USB differential transceiver(positive) I/O 23 18 DM High-speed USB differential transceiver(negative) I/O 25 20 PHY reference resistor input pin. Connect 1. 6K s2 1% resistor to RREF ground, provides reference voltage to USB2 PHY. 27 21 TODN Super speed USB transmitter differential pair(negative) 31 24 TODP Super Speed USB transmitter differential pair(positive) 32 25 RIDN Super Speed USB receiver differential pair(negative) 34 27 RIDP Super Speed USB receiver differential pair(positive) 35 28 Copyright Future Technology devices International Limited FT600Q-FT601Q IC DatasheetDatasheet TDI Version 1.04 Chi Document no∴:F001118 Clearance No: FTDiT424 2024315,19,3 VCC33 +3.3V power input for chip and internal ldo. 8 +1.0V power output from internal LDO. Connecting to VD10 and DV10 AVDD, with a 4. 7u F cap to ground is recommended 39 31 PWR 30,33,2326 VD10 +1.0V core voltage input. 48 7,50 PWR 1449,53844,5 VCCIO Power input for I/o block supports +1.8/+2.5/+3.3V. 9,68 VDDA +3.3V power input for USB2.0 and USB30 PHYs PWR 28 22 AVDD +1.0V power input for PLL PWR 1 32 GND Ground GND 29,36 4951 Table 3.1 Device pin out signal descriptions Copyright Future Technology devices International Limited 10

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