AN_376 Xilinx FPGA FIFO master Programming Guide.p

文件名称: AN_376 Xilinx FPGA FIFO master Programming Guide.pdf

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详细说明：FT601Q-Xilinx FPGA FIFO master Programming Guide源码FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 1 Introduction This document explains how to use Xilinx program tool imPACT to program Xilinx FPGa as a FIFO master with the sample image for UMFT600X/UMFT601X module 1。1 Overview UMFT600X/UMFT601X modules are evaluation modules with FMC(LPC)high speed connectors, providing a USB30 to 16Bit/32Bit wide parallel FIfo interface which are used to evaluate the functionality of FT600/ FT601 devices As a FIFo slave board the UMFT600X/UMFT601X operates with a FIFo master board which has a standard FMc connector. This document explains how to program a Xilinx FPGA(Spartan-6 FPGA SP601 Evaluation Kit and Virtex-6 LX240T Evaluation Kit)as a FIFo master with the sample image, so that user can run FT600DataLoopbackApp' to verify module's functions 1.2 Prerequisite A PC with Xilinx program tool iMPACT(Assume Xilinx drivers have been installed. Xilinx Spartan-6 FPGA SP601 evaluation Ki Xilinx virtex-6 LX240T FPGA HTG-V6-PCIE Evaluation kit and platform cable usb ii 1.3 Notes FTDI provides 8 different fPga loopback application images and 2 PCb evaluation boards with an HSMc connector that is compatible with xilinx FPGa development kits. Ensure the FPGA image used, matches with the pcb evaluation board i. e. umft600 or UMFt601 and either 600 mode or 245 mode of operation Data transfer will not work properly if the fPga image is incompatible with the pcb evaluation board FPGA loopback application images Xilinx FPGA-Spartan-6 SP601 FT601, 600 mode Xilinx FPGA-Spartan-6 SP601, FT601, 245 mode Xilinx FPGA-Virtex-6 HTG-V6-PCIE, FT601, 600 mode Xilinx FPGA-Virtex-6 HTG-V6-PCIE FT601, 245 mode Xilinx FPGA-Spartan-6SP601 FT600, 600 mode Xilinx FPGA-Spartan-6 SP601, FT600, 245 mode Xilinx FPGA-Virtex-6 HTG-V6-PCIE, FT600, 600 mode Xilinx FPGA-Virtex-6 HTG-V6-PClE, FT600, 245 mode PCB evaluation board UMFT601X(HW)-For Xilinx FPGA with FT601 image UMFT600X(HW_431)-For Xilinx FPGA with FT600 image Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 2 Step-by-step instruction 2.1.1 Spartan-6 SP601 1. Connect the SP601 J10(USB J]TAG to a pC with a mini-USB cable, 2. Apply dc5v to ]18, then turn on the poWer (SW1 to ON 3. On the sP601 all SW and Jumpers are configured as default SW2-SPI 4-Exclude SW8 Flash FMC 1-on Short 1-2 1-off 2-0f 2-0n 3-off 4-off USB JTAG SPARTANV.1 aAu x20250u I eaTs POWER SW e 00042502018 USB UART a(2009 xIlInx. Incorporated DCSV IN Figure 2.1 SP601 Hardware Setup Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 4. Run the Xilinx program tool iMPACT, the New iMPACT Project interface will appear, then click Cance to return to the main interface MP△ CT Flow 什口 uH Bour dery Scan Create PROM File ( RCM File format. E New iMPACT PrUjeLL I Warl lu e lead most recant project 32bi:_600M_spartan, pt 3r。wE, E Load most recent project file when iMPACT starts uele d iew w uje_l( un uefaulLipf ■日x Figure 2.2 iMPACT User Interface 5. Double click Boundary scan'at the iMPACT Flows window. 6. Move the mouse pointer to the right side window and right click select Initialize chain 7. The tool will search and find the jtag device automatically Fe IS: iMPACT(P.20-310:3)-Buurndury Scan) E Eile Euit Iew Owe diurs Qulpul Debug Endow Haly -日口回0曲m户e? HH Boundary sycremACF B Create PROM File(P ROM Fie Format. 由自 Weo Talk Data Right click to Add Desire nr initalize ITAG cha +回日 Add XilInx DevIce CtrL+D valah e peration Add Nor-Xiling device. Ctrl+k Cable auto conncet able setup. 冂FX FR* BATCH CMD ge-Mode -be Errors! Warning No Cable Connection No File pen Figure 2.3 Boundary Scan and Initialize Chain Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 8. If iMPACT found the device, click Yes to assign the demo FPga configuration file and specify the sample bit file for the FPGA EB ISE iMPACT(P.20131013-[Boundary Scan I Bs File Edt View Opcrtions Output Debug Window Help □回x 口日0出※非园mp iMPAC" Fows 口× Right click device to select operations Rnurdary Sran 日 SysterACD create PROM hile (FPoM hile ormat 由 ehTalk Data bypass MPAC Proc是35 Ayailable Aeration are Identify succeeded Ee Auto Assign Configu ation Files Quey Dialog /** BATCH C Do you want to continue and assign configuration files(s)? again, save the seting n preference cole F ion Platform Cabl6M「[b+ Figure 2.4 Found Device 9. The selected bit file will be shown in the device window 10. The Flash PROMs interface will now appear. 11. Click Yes' to program SPi flash or click No'to skip and program the FPga only. E 'EL iMPACT(P 2013_013)-[Bounday Scar] Pe File Ecit View Operations Ouput Dekug Window Help - Fx iMPACFbAs Right click devine to select operations Boundary Scan a Create PROM File[PROM File Farmat ACrC Attach SPi or bPI PROM Dav ir-sigratI 命 Read perice ona 2 Ds eunt h d r O M hi dere ded 日 ---------------- 目csEs|上W Configuration Platform Cable USB5 u: b-fs Figure 2. 5 Assign FPGA configure file successfully Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 12. After specifying the. mcs files the interface shown below will appear 13. Select"SPI PROM"and Flash select W25Q64FV data width select 1 ACT (P. 20131013)-[Bourdary Scan] Re Eile Edit Yiew Operations Qutput Debug Wir dow Help iYPACT FluEs 艹□日X Tight click device to select 由 Buuniudly SLc 目Stem E Create PRCM File(PF.OM File Format 自 WebTalkc Data Ito rst to2 bit MMPACTPnocc3EO Select Attached SPlB-Jl Awalab E Operations are 艹口白X 一一一一一 rrer sb-t Figure 2.6 assigning File for Flash and select flash type 14. Select FLASHor Xilinx fPga device then double click Programfor programming SPI flash or fpga RIS- iMPACT (P. 20: 31012)-[Boundary Scanl 5 Cile Idit yiew Cperations Qut put Debug Window Llel 口日0x目品回卫怕 MFACT Flows stons 日雷 undary5an SystemACE Create Prov file prom file format. cost 15 MPACT Processes Available Operatics are: D Verify ● Erase 令 Clank check Readback c GEt Device Checksum 令[ cad derise statu5 Buulat y Scd Console ■p风 Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 多上e上 It vIe partons旦 utput Debug Window Hels b目的自目吗m卢吧 MPACT FI 艹日卢 H Boundary Scan 自5ye a Crea: e P< M Hle(PHOPAHlie bormat 日国 WebTalk date fo met top brt MPAC T Processes C OnlESLEW SVF 中 Reac Deice DNA BouriLdy s_arl 〓百 sa7aLab1 e for t8→abL1÷ Errare! Warnings Configurat rr Flatform cahlE USR& MHz nch-f Figure 2.7 Select Program Device 15. Information message 'Program Succeeded will be shown after programing successfully Re ISE MFACT (P. 20131013)-[Boundary Scanl E Eile Edit View 2回的自x出a盖!缺回mp IMAC:-loNs ˉ7| Rght click device to select operations Create fRoM File (proM File Format 由 Web talk data H二日x edildtle overslip≥ → Program ProgruInl Succeeded → Read device status 围 oundary scan 4□x Elapsed =ime 11 sec 目cms f warnings Configura Form Cable JSB 6MHz Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference Ft 001193 Clearance No. FTDI#462 Ee ISE iMPACT(P. 20131013)-'Euuriuary Sunil 8 Eile Edit yeN Operations Qutput Debug Window Help □-a 口日哈xH日目少 E Crcatc PROMElc inOM -ilc Format 由 WebTalk Data PACI Processes Available oper 命 Progran →→→→一 Program Succeeded ● Read Device DN Boundar/ Scan 目cnre warnings (ont guration Flatform hle USk6MH7ush-tc Figure 2.8 Program Successfully 2.12 Virtex-6 LX24T HTG-V6-PCIE 1. Connect the "Platform Cable USB II"to the HTG-v6-PCIE 335 JTAG) with the JTAG cable, and connect to a PC with a USB2.0 cable Plug in DC12V to J11, and then turn on POWer (SW11). The HTG-V6-PCiE uses default setting SXILINX USB TO PC Platform Cable USB Il SGNaL e Cer Caid e Madel DLC1C XU-29046 H POWER SW 晶。-鬚-i DC12V IN Figure 2. 9 HTG-V6-PCIE Hardware Setup 9 Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited FTDI AN 376 Xilinx FPGA FIFo master Programming Guide Chip Version 1.0 Document Reference No. ft 001193 Clearance No. FTDI#462 2. The procedures of programming FPga LX240T or Flash are same as section 2.1.1, but the files for FPGa and Flash are different the flash type is 'BPI and the flash model is 28F256P30 with a data width of 16 r(P201:=)-[Boundary Scar] 口回出出盏非卢怕 MPACT =bs Create PRoM File(PrOM File Format u 4= Web lalk Data st-top hit Select Attached SpTBpI Available C perations arei BPI FROM 23F256P30 Cancel Figure 2.10 HTG-V6-PCIE Flash Selection 10 Product Page Document feedback Copyright o 20 15 Future Technology Devices International Limited

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