EFR32FG1-DataSheet-876878.pdfEFR32FG1芯片使用手册3.9.4 D

文件名称: EFR32FG1-DataSheet-876878.pdf

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详细说明：EFR32FG1芯片使用手册3.9.4 Digital to Analog Current Converter(IDAC) 3. 10 Reset Management Unit (RMU) 11 3.11 Core and memory 3.11.1 Processor core 3.11.2 Memory System Controller(MSC) 3.11.3 Linked Direct Memory Access Controller(LDMA) 3.12 Memory Map 12 3.13 Configuration Summary 4. Electrical Specifications 14 4.1 Electrical characteristics 14 4.1.1 Absolute Maximum Ratings 4.1.2 Operating Conditions 4.1.2.1 General Operating Conditions 17 4.1.3 Thermal Characteristics 4.14 DC-DC Converter 4.1.5 Current Consumption 4.1.5.1 Current Consumption 3. 3 V without DC-DC Converter 21 4.1.5.2 Current Consumption 3. 3 V using DC-DC Converter 4.1.5.3 Current Consumption 1.85 V without DC-DC Converter 4.1.5.4 Current Consumption Using Radio 25 4.1.6 Wake up times 27 4.1.7 Brown out detector 27 4.1. 8 Frequency Synthesizer Characteristics 419 24 GHz RF Transceiver characteristics 29 4.1. 9.1 RF Transmitter General characteristics for the 2. 4 ghz band 29 4.1.9.2 RF Receiver General characteristics for the 2 4 GHz Band 4.1.9.3 RF Transmitter Characteristics for 1 Mbps 2GFSK in the 2.4 GHz Band 4.1.9. 4 RF Receiver Characteristics for 1 Mbps 2GFSK in the 2. 4 GHz Band 32 4.1.9.5 RF Transmitter Characteristics for 802. 15.40-QPSK DSSS in the 2.4 ghz band 34 4.1. 9.6 RF Receiver Characteristics for 802.15. 4o-QPSK DSSS in the 2.4 GHz Band 37 4.1.10 Sub-GHz RF Transceiver Characteristics ..39 4.1.10.1 Sub-GHz RF Transmitter Characteristics in the 915 MHz band 40 4110.2 Sub-GHz RF Receiver Characteristics in the 915 mHz Band 44 4.1.10.3 Sub-GHz RF Transmitter Characteristics in the 868 MHZ Band 47 4.1.10.4 Sub-GHz RF Receiver Characteristics in the 868 MHz Band .48 4.1.10.5 Sub-GHz RF Transmitter Characteristics in the 490 mHz band 50 4.1.10.6 Sub-GHz RF Receiver Characteristics in the 490 MHz Band 4.1.10.7 Sub-GHz RF Transmitter Characteristics in the 433 MHz band 4.1.10.8 Sub-GHz RF Receiver Characteristics in the 433 MHz Band .56 4.1.10.9 Sub-GHz RF Transmitter Characteristics in the 315 mhz band 59 4.1.10.10 Sub-GHz RF Receiver Characteristics in the 3 15 mHz band 62 4.1.10.11 Sub-GHz RF Transmitter Characteristics in the 169 mHz band 64 4.1.10.12 Sub-GHz RF Receiver Characteristics in the 169 MHz band 65 4.1.11 Modem Features 4.1.12 Oscillators 67 4.1.12.1LFXO .67 4.1.12.2HFXO 68 4.1.12.3 LERCO 68 4.1. HERCo and AUXHFRco 6 silabs. com Building a more connected world Rev. 1.1 4.1.125 ULFRCO 69 4.1.13 Flash Memory Characteristics 70 4.1.14GPO 71 4.1.15VMON 4.1.16ADC 73 4.1.17|DAC 76 4.1.18 Analog Comparator(ACMP) 4.1.19|2C 80 4.1.20 USART SPI 83 4.2 Typical Performance Curves 84 4.2. 1 Supply Current 85 42.2 DC-DC Converter 87 4.23 Internal Oscillators 89 4.2.42.4GHz Radio 5. Typical Connection Diagrams 97 5.1 Power 97 5.2 RF Matching Networks 99 5.3 Other Connections 100 6. Pin definitions 101 6.1 EFR32FG1 QFN48 Sub-GHz Definition 101 6.1.1 EFR32FG1 QFN48 Sub-GHz GPIO Overview 113 6.2 EFR32FG1 QFN482.4 GHz Definition 114 6.2.1 EFR32FG1 QFN48 2.4 GHz GPIO Overview .,126 6.3 EFR32FG1QFN48.4 GHz and sub-GHz Definition 127 6.3.1 EFR32FG1 QFN48 2.4 GHz and Sub-GHz GPIO Overview 138 6.4 EFR32FG1 QFN32 2.4 GHz Definition 139 6.4.1 EFR32FG1 QFN32 2.4 GHz GPIO Overview 146 6.5 EFR32FG1 QFN32 Sub-GHz Definition 147 6.5.1 EFR32FG1 QFN32 Sub-GHz GPIO Overview .154 6.6 Alternate Functionality Pinout .155 6.7 Analog Port(APORT)Client Maps 161 7. QFN48 Package Specifications 165 7.1 QFN48 Package Dimensions 165 7.2 QFN48 PCB Land Pattern 167 7.3 QFN48 Package Marking 169 8. QFN32 Package specifications 170 8.1 QFN32 Package Dimensions 170 8.2 QFn32 PCB Land Pattern 172 8.3 QFN32 Package Marking 174 9. Revision History 175 silabs. com Building a more connected world Rev. 1.1 9.1 Revision 1.1 175 9.2 Revision 1.0 175 9. 3 Revision 0.97 175 9. 4 Revision 0.951 175 9.5 Revision 0.95 176 9. 6 Revision o 9 176 9.7 Revision 0.81 9.8 Revision o 8 176 silabs. com Building a more connected world Rev. 1.1 EFR32FG1 Flex Gecko Proprietary Protocol Soc Family Data Sheet Feature List 1. Feature List The efR32FG1 highlighted features are listed below Low Power Wireless System-on-Chip Wide selection of MCU peripherals High Performance 32-bit 40 MHz ARM Cortex-M4 with 12-bit 1 Msps SAR Analog to Digital Converter(ADC) DSP instruction and floating- point unit for efficient signal 2x Analog Comparator(ACMP) processing Digital to Analog Current Converter(IDAC) Up to 256 kB flash program memory Up to 32 pins connected to analog channels(APORT) Up to 32 kB RAM data memory shared between Analog Comparators, ADC, and IDAC 2.4 GHz and Sub-GHz radio operation Up to 32 General Purpose I/o pins with output state reten- · Transmit power tion and asynchronous interrupts 2.4 GHz radio: Up to 19.5 dBm 8 Channel dma controller Sub-GHz radio: Up to 20 dBm 12 Channel Peripheral Reflex System(PRS) Low Energy Consumption 2x16-bit Timer/Counter 8. 7 mA RX current at 2, 4 GHz 3+ 4 Compare/Capture/PWM channels 8.2 mA TX current o dBm output power at 2. 4 GHz 32-bit real time counter and calendar 8. 1 ma RX current at 868 MHz 16-bit Low Energy Timer for waveform generation 34.5 mA TX current 14 dBm output power at 868 MHZ 32-bit Ultra Low Energy Timer/Counter for periodic wake-up 63 HAMHz in Active Mode(EMO) from any Energy Mode 1.4 HA EM2 DeepSleep current (full RAM retention and 16-bit Pulse Counter with asynchronous operation RTCC running from LFXO Watchdog Timer with dedicated Rc oscillator 50nA 0.58 HA EM4H Hibernate Mode(128 byte RAM retention 2X Universal Synchronous/ Asynchronous Receiver/Trans Wake on Radio with signal strength detection, preamble mitter(UART/SPI/SmartCard(Iso 7816)IrDAl-S) pattern detection, frame detection and timeout LOW Energy UART (LEUART) High Receiver Performance 12C interface with SMBus support and address recognition -g4 d bm sensitivity 1 Mbit/s GFSK(2. 4GHz in EM3 Stop 121. 4 dBm sensitivity at 2. 4 kbps gFsK(868 MHz) · Wide Operating range Supported Modulation Formats 1.85 V to 3.8 V single power supply 2-FSK/4-FSK with fully configurable shaping Integrated DC-DC, down to 1.8V output with up to 200 mA Shaped OQPSK/(G)MSK load current for system Configurable DSSS and FEC ·-40°Cto85°C BPSK/DBPSK TX QFN32 5x5 mm Package ·OOK/ASK QFN48 7x7 mm Package Supported Protocols Proprietary protocols ·Wre|essM-Bus Low Power wide area networks Support for Internet Security General Purpose CRC Random number generation Hardware Cryptographic Acceleration for AES 128/256 SHA-1, SHA-2 (SHA-224 and SHA-256)and ECC silabs. com Building a more connected world Rev. 1.1 I EFR32FG1 Flex Gecko Proprietary Protocol Soc Family Data Sheet Ordering Information 2. Ordering Information Ordering Code Protocol Stack Frequency Band Flash RAM GPIo Package (KB)(KB) Max TX Power EFR32FG1P133F256GM48-CO Proprietary 24GHz195dBm256 32 28 QFN48 Sub-GHz 20 dBm EFR32FG1P133F128GM48-C0 Proprietary ·24GHz19.5dBm 128 QFN48 Sub-GHz 20 dBm EFR32FG1P133F64GM48-C0 Proprietary 2. 4 GHz 19.5 dBm 64 28 QFN48 Sub-GHZ 20 dBm EFR32FG1P132F256GM48-C0 Proprietary 2.4 GHz 19.5 dBm 256 32 31 QFN48 EFR32FGIP132F128GM48-C0 Proprietary 2. 4 GHz 19.5 dBm 128 32 31 QFN48 EFR32FG1P132F64GM48-C0 Proprietary 2.4 GHz 19.5 dBm 64 16 QFN48 EFR32FG1P132F256GM32-C0 Proprietary 2. 4 GHz 19.5 dBm 256 32 16 QFN32 EFR32FGIP132F128GM32-C0 Proprietary 2. 4 GHz 19.5 dBm 128 32 16 QEN32 EFR32FG1P132F64GM32-C0 Proprietary 2. 4 GHz 19.5 dBm 64 16 16 QFn32 EFR32FG1P131F256GM48-CO Proprietary Sub-GHz 20 dBm 256 32 QFN48 EFR32FG1P131F128GM48-C0 Proprietary Sub-GHz 20 dBm 128 32 32 QFN48 EFR32FG1P131F64GM48-C0 Proprietary Sub-GHz20 dBm 64 16 32 QFN48 EFR32FG1P131F256GM32-CO Proprietary Sub-GHz 20 dBm 256 32 16 QFN32 EFR32FG1P131F128GM32-C0 Proprietary Sub-GHZ 20 dBm 128 16 QFN32 EFR32FG1P131F64GM32-CO Proprietary Sub-GHz 20 dBm 16 16 QFN32 EFR32FG1V132F256GM48-C0 Proprietary 2. 4 GHz 16.5 dBm 256 32 31 QFN48 EFR32FG1V132F128GM48-C0 Proprietary 2. 4 GHz 16.5 dBm 128 16 31 QFN48 EFR32FG1V132F64GM48-C0 Proprietary 2. 4 GHz 16.5 dBm 64 16 31 QFN48 EFR32FG1V132F32GM48-C0 Proprieta 2. 4 GHz 16.5 dBm 32 8 QFN48 EFR32FG1V132F256GM32-C0 Proprietary 2. 4 GHz 16.5 dBm 256 32 16 QFN32 EFR32FG1V132F128GM32-CO Proprietary 2. 4 GHz 16.5 dBm 128 16 16 QFN32 EFR32FG1V132F64GM32-CO Proprietary 2. 4 GHz 16.5 dBm 64 16 16 QFN32 EFR32FG1V132F32GM32-C0 Proprietary 2. 4 GHz 16.5 dBm 32 16 QFN32 EFR32FG1V131F256GM48-C0 Proprietary Sub-GHz 16.5 dBm 256 32 32 QFN48 EFR32FG1V131F128GM48-C0 Proprietary Sub-GHz 16.5 dBm 128 16 32 QFN48 EFR32FG1V131F64GM48-C0 Proprietary Sub-GHz 16.5 dBm 64 16 32 QFN48 EFR32FG1V131F32GM48-C0 Proprietary Sub-GHz 16.5 dBm 32 8 32 QFN48 EFR32FG1V131F256GM32-C0 Proprietary Sub-GHz 16.5 dBm 256 32 16 QFN32 EFR32FG1V131F128GM32-CO Proprietary Sub-GHz 16.5 dBm 128 16 16 QFN32 EFR32FG1V131F64GM32-C0 Proprietary Sub-GHz 16.5 dBm 64 16 16 QFN32 EFR32FG1V131F32GM32-CO Proprietary Sub-GHz 16.5 dBm 32 8 16 QFN32 EFR32FG1V032F256GM32-C0 Proprietary 2.4 GHZ 8 dBm 256 16 QFN32 silabs. com Building a more connected world Rev.1.1|2 EFR32FG1 Flex Gecko Proprietary Protocol Soc Family Data Sheet Ordering Information Ordering Code Protocol stack Frequency Band Flash RAM GPIO Package (kB)(kB) Max TX Power EFR32FG1V032F128GM32-C0 Proprietary 2. 4 GHz 8 dBm 128 16 QFN32 EFR32 IXG1PI132F1256GM32-COR Tape and Reel(option Revision Pin Count Package-M(QFN), J(CSP) Temperature Grade-G(-40to+85°℃),l(-40to+125°c) Flash Memory Size in kB Memory Type(Flash) Feature Set Code-r2rirO r2: Reserved r1: RF Type-3 (TRX), 2(RX), 1(TX) rO: Frequency Band -1 (Sub-GHz), 2(2.4 GHz), 3 (Dual-Band Performance Grade-P(Performance),B (Basic),V(Value) erles Family-M(Mighty), B(Blue),F(Flex) Wireless gecko 32-bit Figure 2.1. OPN Decoder silabs. com Building a more connected world Rev.1.1|3 EFR32FG1 Flex Gecko Proprietary Protocol Soc Family Data Sheet System Overview 3. System Overview 3.1Introduction The EFR32 product family combines an energy-friendly MCu with a highly integrated radio transceiver the devices are well suited for any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a short introduction to the full radio and mcu system the detailed functional description can be found in the eFr32 Reference Manual a block diagram of the EFR32FG 1 family is shown in Figure 3. 1 Detailed EFR32FG1 Block Diagram on page 4. The diagram shows a superset of features available on the family, which vary by OPn. For more information about specific device features, consult Ordet ing Information Radio Transciever Port I/O Configuration Sub-GHZ RF SUBGRE|P凶 LNA SUBGRF IN Digital Peripherals subGRE O LETIMER SUBGRE ONⅨ IFADC IOVDD TIMER RFSENSE 2.4 GHz RF Frequency AGC CRYOTIMER Synthes izer 2G4RFOPⅨ4 BALN凵 MOD PCNT Port A 2G4RF|ON区 Circuite Drivers RTC/RTCC M Energy M ARM Cortex-M4 Core PAVDD X LEUART Port B Up to 256 KB ISP Flash Drivers 区PBn REVDD区 Program Memory 12C IOVDD X Up to 32 KB RAM CRYPTO 区 Voltage A Monito Memory Protection Unit CRC rIvers DVDD区 Floating Point Unit b DMA Controller DD区 Analog Peripherals Port D DC-DC Voltage Serial Wire Debug Drivers 区PD VREGSW H Converter Regulator DECOUPLE区 Referen m Interna IDAO Watchd。g Timer VDD EF Port F Drivers →冈PFn VREGVSS区 Brown Out/ Clock Management VDD RFVSSⅨ er PAVSSⅨ Reset 12-bit ADC ULFRCO Reset AUXHFRCO RESETn区 Management Unit FRCO Temp Sensor HFRCO LEXTAL P/N LEXO HEXTAL_P区 HFXO HEXTAL N区 Analog Comparator Figure 3.1. Detailed EFR32FG1 Block Diagram 3.2 Radio The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols silabs. com Building a more connected world Rev.1.1|4 EFR32FG1 Flex Gecko Proprietary Protocol Soc Family Data Sheet System Overview 3.2.1 Antenna Interface The EFR32FG 1 family includes devices which support both single-band and dual-band rF communication over separate physical RF interfaces The 2. 4 GHz antenna interface consists of two pins(2G4RF loP and 2G4RF loN) that interface directly to the on-chip balun. the 2G4RF ion pin should be grounded externally The sub-GHz antenna interface consists of a differential transmit interface(pins SUBGRF OP and SUBGRF ON) and a differential re ceive interface(pins SUBGRF IP and SUBGRF IN) The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching Networks section 3.2.2 Fractional-N Frequency Synthesizer The EFR32FG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is used in receive mode to generate the Lo frequency used by the down-conversion mixer. It is also used in transmit mode to directly generate the modulated rF carrier The fractional-n architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to optimize system energy consumption 3.2.3 Receiver architecture The EFR32FG 1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier(LNA) followed by an l/Q down-conversion mix er, employing a crystal reference. The l/Q signals are further filtered and amplified before being sampled by the iF analog-to-digital converter(IFADC) The if frequency is configurable from 150 kHz to 1371 kHz. the if can further be configured for high-side or low-side injection provid ing flexibility with respect to known interferers at the image frequency The Automatic Gain Control (AGC)module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec- tivity and blocking performance. The 2. 4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHZ radio can be calibrated on-demand by the user for the desired frequency band Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re ceive bandwidths ranging from 0. 1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by block and convolutional coding as well as direct Sequence Spread Spectrum (DSSS A Received Signal Strength Indicator(RsSI)is available for signal quality metrics, for level-based proximity detection, and for rF chan nel access by Collision Avoidance(CA)or Listen Before Talk(LBT)algorithms. An RSSI capture value is associated with each received frame and the dynamic RssI measurement can be monitored throughout reception The EFR32FG 1 features integrated support for antenna diversity to improve link budget for 802.15.4 DsSS-oQPSK PHY configuration in the 2. 4 GHz band, using complementary control outputs to an external switch Internal configurable hardware controls automatic switching between antennae during RF receive detection operations 3.2.4 Transmitter Architecture The EFR32FG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats the modulator controls phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping filter. The shaping filter is fully configurable, including the bt product, and can be used to implement gaussian or raised cosine shap- Ing Carrier Sense Multiple Access-Collision Avoidance( CSMA-CA)or Listen Before Talk(LBt) algorithms can be automatically timed by the EFR32FG1. these algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be- ween devices that otherwise lack synchronized RF channel access 3.2.5 Wake on radio The Wake on Radio feature allows flexible, autonomous RF sensing qualification, and demodulation without required mcu activity, us ing a subsystem of the EFR32FG1 including the Radio Controller(RAC ), Peripheral Reflex System(PRS), and Low Energy peripherals silabs. com Building a more connected world Rev. 1.1 I

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