ADRF6516-879737.pdfADRF6516芯片使用手册Data sheet ADRF65

文件名称: ADRF6516-879737.pdf

所属分类: 硬件开发

开发工具:

文件大小: 1mb

下载次数: 0

上传时间: 2019-08-24

提供者: weiyung*******

下载 (1mb)

不能下载？报告错误

详细说明：ADRF6516芯片使用手册Data sheet ADRF6516 SPECIFICATIONS VPS=3.3 V, TA= 25C, ZLoAD=1 kQ, digital gain code= 1ll, unless otherwise noted Table 1 Parameter Test Conditions/Comments Min Typ Unit FREQUENCY RESPONSE Low-Pass Corner Frequency, fc 6-pole Butterworth filter 0.5 db bandwidth 31 Step size MHZ Corner Frequency Absolute Over operating temperature range 15 fc Accuracy Corner Frequency Matching Channel a and channel b at same gain and ±0.5 fo bandwidth settings Pass-Band Ripple 0.5 dB p-p Gain Matching Channel a and channel b at same gain and ±0.1 dB bandwidth settings Group Delay variation From midband to peak Corner frequency 1 Mhz 135 Corner Frequency =31 MHZ ns Group Delay Matching Channel a and channel b at same gain Corner frequency =1 MHZ ns Corner Frequency=31 MHz 0.2 ns Stop-Band Rejection Relative to Pass band 2×f 30 dB 5×fε 75 dB INPUT STAGE INP1, INMI, INP2, INM2, VICM pins Maximum Input swing At minimum gain, VGAIN=OV Vp-p Differential Input Impedance 1600 Input Common- Mode range 0. 4V p-p input voltage, HD3>65 dBc 1.65 1.8 Input pins left floating VPS/2 VICM Output Impedance GAIN CONTROL GAIN pin Voltage gain Range VGAIN from oV to 1 V +45 Gain Slope 15.5 mV/dB Gain error VGAin from 300 mV to 800 mV 02 dB OUTPUT STAGE OPP1, OPMl, OPP2, OPM2, VOCM pins Maximum Output Swing At maximum gain, RLOAu=1 kQ2 V p-p HD2>65 dBc hD3 >65 dBc 1.5 Vp-p Differential Output Impedance 30 Output DC Offset Inputs shorted offset loop disable Output Common-Mode range 07 1.65 2.8 VOCM pin lett floating VPS/2 VOCM Input Impedance 23 k NOISE/DISTORTION Corner Frequency=1 MHz Output Noise Density Gain=o dB at fc/2 -141 dBV/Hz Gain =20 dB at f/2 -131 d BV/VHz Gain= 40 dB at fc/2 112 dBV√VHz Second harmonic HD2 250 kHz fundamental, 1.5 v p-p output voltage Gain=5 dB 82 d Bc Gain= 40 dB d Bc Third harmonic, HD3 250 kHz fundamental, 1.5v p-p output voltage Gain=5 dB 71 Gain=40 dB 56 d Bc C Page 3 ADRF6516 Data sheet Parameter Test Conditions/Comments Min Typ Max Unit IMD3 f1=500 kHz, f2=550 kHz, 1.5Vp-p composite utput volt Gain=5 dB 61 C Gain =35 dB 42.5 IMD3 with Input Cw blocker f1=500 kHz, f2=550 kHz, 1.5V p-p composite d Bc output, gain=5 dB; blocker at 5 MHz, 10 dBc 'e to two-tone composite output voltag Corner Frequency =31 MHz Output Noise density Midband, gain=0 dB 143.5 dBV/vHz Midband gain =20 dB -139 dBV/vHz Midband, gain =40 dB -125 dBV/vHz Second harmonic, hd2 8 MHz fundamental, 1.5 v p-p output voltage Gain=5 dB 68 d Bc Gain= 40 dB d Bc Third Harmonic, HD3 8 MHz fundamental, 1.5V p-p output voltage Gain=5 dB 55 d Bc Gain= 40 dB IMD3 f1=14 MHZ, f2=15 MHz, 1.5V p-p composite output voltage Gain=5dB 55 d Bc Gain =35 dB 775 dBc IMD3 with Input CW blocker f1=14 MHz, f2=15 MHz, 1.5V p-p composite 55 dBc output, gain=5 dB; blocker at 150 MHz, 10 dBc relative to two-tone composite output voltage DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS pins Input High Voltage, VINH Input Low Voltage, VINI <0.8 Input Current IINH/INL <1 nput Capacitance, CIN F SPI TIMING LE, CLK, DATA, SDO pins(see Figure 2 and Figure 3) fs 1/t sCLK 0 MHz data hold time DATA setup time tuh le hold time 225555 S tls LE setup time tp CLK high pulse width ns CLk to sdo delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL pins Supply voltage range 3.15 3.3 Total Supply Current ENBL=3.3V Corner frequency =31 mhz 360 Corner frequency= 1 MHZ 330 n Disable current ENBL=OV 9 MA Disable threshold 1.6 Enable Response Time Delay following ENBL low-to-high transition Disable Response Iime Delay following ENBL high-to-low transition 300 nS Rev. c Page 4 of 29 Data sheet ADRF6516 TIMING DIAGRAMS Figure 2. Write Mode Timing Diagram Figure 3. Read Mode Timing Diagram C Page 5 of ADRF6516 Data sheet ABSOLUTE MAXIMUM RATINGS Table 2 Stresses at or above those listed under absolute maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Supply Voltages, VPS, VPSD 3.45V stress rating only; functional operation of the product at these ENBL OFDS, LE, CLK, DATA, SDO /PSD+0.5V or any other conditions above those indicated in the operational INP1, INMT, INP2, INM2 /PS+0.5V section of this specification is not implied. Operation beyond OPP1, OPM1 OPP2, OPM2 VPS +0.5v the maximum operating conditions for extended periods may OFS1 OFS2 VPS+0.5v affect product reliabilit GAIN /PS+0.5V ESD CAUTION Internal Power Dissipation 1.25W ESD (electrostatic discharge) sensitive device. BJA (Exposed Pad Soldered to boa 37.4°C/V Charged devices and circuit boards can discharge Maximum Junction Temperature 150°C without detection. Although this product features Operating Temperature Range 40°cto+85°C patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD Storage temperature range -65°Cto+150C Thercfore, proper ESD precautions should be taken to Lead Temperature(Soldering 60 sec) 300°C avoid performance degradation or loss of functionality Rev. c Page 6 of 29 Data sheet ADRF6516 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Fiqure 4 Pin Confiquration Table 3 Pin Function Descriptions Pin no Mnemonic Description VPSD Digital Positive Supply voltage: 3.15V to 3. 45 V. COMD Digital Common. Connect to external circuit common using the lowest possible impedance LE Latch Enable SPl programming pin TtL levels: VLOw<0.8 V, VHIGH>2V CLK SPI Port Clock. TTL levelS: VLOW<0.8 V, VHIGH > 2V DATA SPI Data Input. ttL levels: VLOW <0.8V, VHIGH>2V SDO SPl Data Output. TtL levels: VLOw<0.8 V, VHIGH>2 V 7913,19,22,28coM Analog common Connect to external circuit common using the lowest possible impedance. 8,1216,2529VPs Analog positive Supply voltage: 3.15v to 3.45 V. 10,11,30,31 INP2 NM2 Differential Inputs 1600 Q input impedance INM1 NP1 OFDS Offset Compensation Loop Disable. Pull high to disable the offset compensation loop 15,26 OFS2 OFS1 Offset Compensation Loop Capacitors. Connect capacitors to circuit common 17,18,23,24 OPP2, OPM2 Differential Outputs. 30 Q2 output impedance. Common-mode range is 0.7V to 2.8 V; default is VPS/2. OPM1, OPP1 VOCM Output Common -Mode Setpoint. Defaults to VPS/2 if left floating 2 GAiN Analog Gain Control. OV to 1V,15.5 mv/dB gain scaling 27 VICM Input Common-Mode Voltage. VPS/2V reference. Use to reference the optimal common-mode drive to the differential inputs ENBL Chip enable. Pull high to enable EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad C Page 7 of ADRF6516 Data sheet TYPICAL PERFORMANCE CHARACTERISTICS VPS=3.3 V, TA=250C, ZLOAD=1 kQ2, digital gain code =lll, unless otherwise noted Figure 5. In-Band Gain VS. VGAIN over Supply and Temperature igure8 Gain Conformance Vs VGAIN over Supply and Temperature (Bandwidth Setting=31 MHz) (Bandwidth Setting= 31 MHz) Figure 6. Gain vs Frequency over VGAiN (Bandwidth Setting=37 MHz) Figure 9. Gain Step and Gain Error Vs Frequency (Bandwidth Setting=37 MH Figure 7. Gain Matching vs VGAIN( Bandwidth Setting= 37 MHz) Figure 10. Gain Step and Gain Error vs Frequency (Bandwidth Setting= 31 MHZ, VGAIN=0 V) Rev. c Page 8 of 29 Data sheet ADRF6516 igure 11. Output P1dB vs Gain at 15 MHz (Bandwidth Setting =31 MHz) Figure 14 Frequency Response over Supply and Temperature (Bandwidth Setting 31 MHz, Gain=30 dB) AINNNTMIMMWT Figure 12. Frequency Response vs Bandwidth Setting(Gain=30 dB, Figure 15. Group Delay vs Frequency (Gain=20 dB) Log scale Figure 13 Frequency Response vs Bandwidth Setting(Gain=30 dB), Figure 16 Group Delay Matching vs Frequency Linear scale (Bandwidth Setting=31 MHz) C Page 9 of ADRF6516 Data sheet Figure 17 /Q Group Delay Matching vs Frequency (Bandwidth Setting=1 MHz) (Band gure 20 HD2 vS Gain over Output Common-Mode Voltage width Setting=31 MHz, 1.5V p-p, 8MHz CW Fundamental Output Figure 18 /Q Amplitude Matching vs Frequency Figure 21. HD3 vS Gain over Supply and Temperature (Bandwidth Setting=31 MHz, 1.5 Vp-p, 8 MHz CW Fundamental Output igure 19 HD2 vS Gain over Supply and Temperatur Figure 22 HD3 vS Gain over Output Common-Mode volta (Bandwidth Setting =31 MHz, 1.5Vp-P, 8 MHz CW Fundamental Output) (Bandwidth Setting=31 MHz, 1.5Vp-P, 8 MHz CW Fundamental Output Rev. C Page 10 of 29

(系统自动生成,下载前可以参看下载内容)