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详细说明：64m flash芯片，数据手册，，英文版，页数 6111.2.3 Instruction Set Table 2(Read Instructions)..
19
11.2.4 Write Enable(06h)
11.2.5 Write Disable(04h)
20
11.2.6 Read Status Register-1(05h)and Read Status Register-2 (35h
11.2.7 Write Status Register(01h)
11.2.8 Read Data(03h)
23
11.2.9 Fast Read (OBh).
11.2. 10 Fast Read Dual Output (3Bh)
5
11.2.11 Fast Read Quad Output(6Bh
.26
11.2.12 Fast Read dual l/o(BBh)
27
11.2.13 Fast Read Quad Io(EBh)
11214 Octal Word Read Quad vo(E3h)……
11.2.15 Page Program(02h)
11.2.16 Quad Input Page Program (32h
.34
11.2.17 Sector Erase(20h)
1121832 KB Block erase(52h)……
1121964 KB Block erase(D8h)……
37
11.2.20 Chip Erase(CTh /60h)
““
38
11.2.21 Erase Suspend (75h)
112.22 Erase resume(7Ah)……
.40
11223 Power-down(B9h)……
41
11.2.24 High Performance Mode(3h)
42
11.2.25 Release Power-down or High Performance Mode /Device ID(ABh)......... 42
11.2.26 Read Manufacturer /Device ID (90h)
44
11.2. 27 Read Unique ID Number(4Bh)
45
11.2.28 Read JEDEC ID(9Fh)
46
11.2. 29 Continuous Read Mode Reset(FFh or FFFFh
47
12
ELECTRICAL CHARACTERISTICS
48
12.1 Absolute Maximum Ratings
48
122 Operating Ranges…
48
12.3 Power-up Timing and Write Inhibit Threshold
49
12.4 DC Electrical Characteristics
125 AC Measurement conditions
12.6 AC Electrical characteristics
面日1B
52
12.7 AC Electrical Characteristics(contd
53
128 Serial Output Timing…………
54
12.9 nput Timing…
54
12.10 Hold Timing…
54
13. PACKAGE SPECIFICATION
55
13.1 8-Pin SOIC 208-mil(Package Code SS)
55
1328- Pin pdip300-mi( Package Code DA)……
56
13.38c。 ntact8x6 mm WsoN( ackage C。 ode ze).
57
13.4 16-Pin SOIC 300-mil (Package Code SF)
58
14
ORDERING INFORMATION
59
14.1 Valid Part Numbers and Top Side Marking
60
15. REVISION HISTORY
6
1. GENERAL DESCRIPTION
The W25Q64BV(64M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary seria
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPl
(XIP)and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with
current consumption as low as 4mA active and 1ua for power-down. all devices are offered in space-
saving packages
The W25Q64BV array is organized into 32, 768 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB
block erase), groups of 256(64KB block erase) or the entire chip(chip erase). The W25Q64 BV has 2, 048
erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility
in applications that require data and parameter storage. (See figure 2
The W25Q64BV supports the standard Serial Peripheral Interface (SPl), and a high performance
Dual/Quad output as well as dual/Quad l/O SPl: Serial Clock, Chip select, Serial Data 1O0(DD,l/0
(DO),I/O2(/WP), and 1/03(HOLD). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Fast
Read dual/Quad output instructions. these transfer rates can outperform standard asynchronous 8 and
16-bit Parallel Flash memories. The Continuous read mode allows for efficient memory access with as
few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XiP (execute in place
operation
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification with a 64-bit Unique serial Number
2. FEATURES
Family of SpiFlash Memories
Low Power, Wide Temperature range
W25Q64BV:64M-bit/8 M-byte(8,388,608)
Single 2. 7 to 3.6V supply
256-bytes per programmable page
4mA active current, <1HA Power-down(typ.
Standard. dual or quad sP
-40°Cto+85° operating range
Standard SPl: CLK/CS. DI do. /P/Hold
Flexible architecture with 4KB sectors
Dual SPl: CLK, /CS, IOo, Io,,/P, /Hold
Uniform Sector Erase( 4K-bytes
Quad SPl: CLK, /Cs, IOo, IO1, 102, IO 3
Block Erase(32K and 64K-bytes
Highest Performance Serial Flash
Program one to 256 bytes
More than 100,000 erase/write cycles
Up to 6x that of ordinary serial Flash
More than 20-year data retention
80MHZ clock operation
160MHz equivalent Dual SP
Advanced Security Features
320MHz equivalent Quad SPl
Software and Hardware Write-Protect
40MB/S continuous data transfer rate
Top or Bottom, Sector or Block selection
Lock-Down and otP protection
1)
● Efficient“ Continuous read mode”
64-Bit Unique ID for each device
Low Instruction overhead
as few as 8 clocks to address memo
Space Efficient Packaging
Allows true XIP (execute in place)operation
8-pin SoIC 208-mil
Outperforms X16 Parallel Flash
8-pin PDiP 300-mil
8-pad WSON 8X6-mm
Note 1: Contact winbond for details
16-pin SoIC 300-mil
Contact Winbond for KGD and other options
3. PIN CONFIGURATION SOIC 208-MIL
/CS
8
VCC
DO (IO1)
/HOLD (IO3
∧WP(02)
CLK
GND
D(○)
Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil( Package Code sS)
4. PAD CONFIGURATION WSON 8X6-MM
1
8( VCC
Do(0)2
7 ( /HOLD(IO3
WP(IO2
6
CLK
GND
5
Figure 1b. W25Q64BV Pad Assignments, 8-pad WSON 8x6-mm(Package Code ZE)
winbond
5. PAD CONFIGURATION PDIP 300-MIL
/CS
8
DO(○1)
2
7
/HOLD (IO3)
∧wP(O2)
CLK
GND
4
DI (IOo)
Figure 1c. W25Q64BV Pin Assignments, 8-pin PDIP(Package Code DA)
6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL AND WSON 8X6-MM
PIN NO
PIN NAME
FUNCTION
/CS
Chip Select Inpu
DO(O1)
10 Data Output(Data Input Output 1)
3
MP(02)
1/0 Write Protect Input( Data Input Output 2)
4
GND
Ground
5
DI (IOO
l/0 Data Input(Data Input Output O)1
6
CLK
Serial Clock Input
/HOLD (IO3
vO
Hold Input (Data Input Output 3*
8
VCC
Power Supply
1 00 and lo1 are used for standard and dual spi instructions
2100-103 are used for Quad SPl instructions
7 PIN CONFIGURATION SOIC 300-MIL
/HOLD (O3)
16
CLK
15
Dl(○)
N/C
14
Nc
13
N/C
N/C
6
N/C
/CS
10
GND
DO (IO)
8
NP(lO2
Figure 1d. W25Q64BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
8. PIN DESCRIPTION SOIC 300-MIL
PAD NO
PAD NAME
vO
FUNCTION
HOLD(103)
Hold Input(Data Input Output 3) *2
2
VCC
Power Supply
N/C
No Connect
N/C
No connect
5
N/C
No Connect
N/C
No Connect
7
/CS
Chip select Input
8
DO(IO1)
O
Data Output ( Data Input output 1)
9
MP(102) o Write Protect Input(Data Input Output 2)2
10
GND
Ground
11
N/C
No Connect
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI (IO0)
10 Data Input( Data Input Output O)*
16
CLK
Serial Clock Input
1 00 and lo 1 are used for standard and dual spl instructions
2100-l03 are used for Quad SPl instructions
8.1 Package Types
W25Q64BV is offered in an 8-pin plastic 208-mil width soic (package code ss)and 8X6-mm WsoN
(package code ZE) as shown in figure 1a, and 1b, respectively. The 300-mil 8-pin PDIP is another option
of package selections(Figure 1c). The W25Q64BV is also offered in a 16-pin plastic 300-mil width SOIC
(package code SF)as shown in figure 1d Package diagrams and dimensions are illustrated at the end of
this datasheet
8.2 Chip Select(CS)
The SPI Chip Select (Cs) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output(DO, or 100, 101, 102,103)pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted
The /Cs input must track the VCC supply level at power-up(see Write Protection"and figure 31). If
needed a pull-up resister on /Cs can be used to accomplish this
8.3 Serial Data Input, Output and lOs(Dl, DO and lo0, 101, 102, 103
The W25Q64BV supports standard SPl, Dual SPI and Quad SPI operation Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock(CLK)input pin standard SPi also uses the unidirectional Do(output) to read
data or status from the device on the falling edge CLK
Dual and Quad SPl instruction use the bidirectional Io pins to serially write instructions, addresses or
data to the device on the rising edge of clk and read data or status from the device on the falling edge of
CLK Quad SPl instructions require the non-volatile Quad Enable bit(QE)in Status Register-2 to be set
When QE=1 the/P pin becomes 102 and/HOLD pin becomes 103
8.4 Write Protect (WP)
The Write Protect (/P)pin can be used to prevent the Status Register from being written. Used
conjunction with the status Register's block Protect (sEC, TB, BP2, BP1 and bpo) bits and status
Register Protect (SRP)bits, a portion or the entire memory array can be hardware protected. The /P
pin is active low. When the Qe bit of Status Register-2 is set for Quad I/O, the /P pin(Hardware Write
Protect)function is not available since this pin is used for 102. See figure la, 1b, 1c and 1d for the pin
configuration of Quad t/o operation
8.5HOLD∥HoLD)
The /HOLd pin allows the device to be paused while it is actively selected. When /HOLD is brought low
while /CS is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored
(don' t care). When/HOLD is brought high, device operation can resume. The /HOLd function can be
useful when multiple devices are sharing the same SPI signals. The /HoLd pin is active low. When the
Qe bit of Status Register-2 is set for Quad I/O, the /HoLd pin function is not available since this pin is
used for 103. See figure 1 a-d for the pin configuration of Quad o operation
8.6 Serial Clock(CLK)
The SPI Serial Clock Input(CLK)pin provides the timing for serial input and output operations. ("See SPl
Operations")
9. BLOCK DIAGRAM
Block Segmentation
■■■画■■国■
xFFOOh
XxFFFFh
7FFF0Oh
7FFFFFh
口口留口口
Sector 15(4KB)
Block 127(64KB)
xxFooOh
XXFOFFh
7Fo00Oh
7F00FFh
XXEFOOh
XXEFFFh I
Sector 14(4KB)
xxOo
XXEOFFh
XXDFOOh
xxDFFFh
Sector 13(4KB)
■■■
xxDOOOh
XXDOFFh
■■■■■■■■■口■■■■口■
xx2 F0Oh
Xx2FFFh
Sector 2(4KB)
xx2000h
(20FFh
xX1 FFFh
40FF0Oh
Xx1F0Oh
40FFFFh
Sector 1(4KB)
lock 64 (64KB)
xx1 OFFh
400000h
4000FFh
3FFFOOh
Sector 0 (4KB)
看日日园口口
Block 63( 64KB)
3F0000h
3F00FFh
∧P(O2)
Write Control
Logic
20FFFFh
Block 32(64KB)
200000h
000FFh
1FFF0Oh
1FFFFFh
Ree
Block 31(64KB)
1F0000h
1F00FFh
High voltage
Generators
00FFoOh
O0FFFFh
HOLD(IO,)
Block 0 (64KB)
000000h
0000FFh
CLK
Latch/Counte
Endi
Page Addres
/CS
Command
Control le
Column Decod
And 256-Byte Page Buffer
○)
DO(IO,)
Byte Add
Latch/ Counter
Figure 2. W25Q64BV Serial Flash Memory Block Diagram
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