英特尔z3735f_sch_MID.pdfintel win8 平板设计参考原理图（双系统）z373

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详细说明：intel win8 平板设计参考原理图（双系统）z3735f_sch_MIDPower Map GO/o GO/S0lx G1/54 G2/55 G3 Powe Device MAX: 2A 1C 0TA MAX: 5 +3PJA ALcO3 MAX: 2R 0.4V~1 AXP288 1.日A TPS2065 NTEL SOC GPIO SWITCH TAX:EA +VRTC +V3P3SX_ALDO2 USB2 LAB V3P3A SDIO so 150A RESERVED 工 NTEL SCC GPIO 4C 0TA ViPs ELD02 +V1PR ANPAK 2C0uA 4VREF DDR V2P8A CLDO1 V3P3A CLCO2 v3P3SX DLDC3 DLDOIN 3C 0A ELDO工N v3P3 DLDo4 MB3422GG EMU SLP OIX N MP3422U22):2n CODEC (U19):0.5A vsP三AK Ax卫288 TPS2065 PMIC TEL SOC GPI SWITCH BAY TRAT一soc DP/DM USB2 uAB INTEL SCC GP工 15 PWRBTN Note A=Battery path B=Usb Adapter path The power on interval of each BUCK/LDo is 1ms Power stats 54/55 to SO Cause of Wake Events Voltage Rail G3 How Enabled Intemal Set PM1_ STS_EN. RTC_EN reg ister bit n off EXternal Default enabled as Wake event -V VNIN On GPIO_S5[7: 0 External GPEOa_EN register(after having gone to s5 v⊥PoA On PM1 CNT SLP EN, but not after a power failure I VISa 口「 Note: GPIOs that are n the core well are not capable of waking the systern from sleep states where the core v1P之A n off well is not powere ME穿十3P3A Internal GPEOa_EN PME_BO_EN register bit. This wake statue on off bit includes multiple intemal agents -1PP5X an off cff EHCI(USB2 PME_B0_s5_DIS bit Ii used to prevent these devices v⊥P山 n o什 from waking from S5 +VDDO on OfT PMC- Initiated Internal No enable bits. The PMC can wake the hos dent of other wake events listed, if desired. A WREH k On OfF bit is provided in PRSTs for reporting this wake event VSDIO On/o tO BIOS. Note that this wake event may be used as a wake trigger cn behalf of some other wake source, +VRTC on n on Processor Core/ States Support SOix Cause of Wake Events General Power States for System Cause T How Enabled States/Sub- state Description I egacy Name description Act ve mode, processor Executing code Any GPIo 16 bit address External Io-APIC forwards the interrupt resulting in SC(as configured by BIOS) Go/50/c0 FULL ON: CPJ operating. Indrvid ual cev ices may be shut down to save ALtohalt stato LPC CLKRUN External wake from s0i2/3 ony when the signal is asserted power. the different CPu cperating levels are defined ty Cx state AlmH AI T state with lowres frequency and voltage operating point moves the soc to so 1 CO/S0/Cx Cx State: CPU manages c-state itcelf. Deep power Down. Prior to enterin g the Deep Power Down GU/S0il SUil state: Low power platform active state. All DRAM and Iost tratr are lechnolcgy (code named Cb) state, I he core process will Flush its PCB Footprints halted, PLL are configured to be off. This state allows MP3 play ing using LPI engine different power plane. Once Deep power Down Technology (code GO/S012 soi2 State: The Soc clocks and oscillators are parked named C6 sequence has completed. The core processors valtage is completely shut off. CO/S013 s0i3 statc: All Soc clocks and cecillatorg arc turned off Execution cores in this state bahave sim larly to the CG state. Suspenul-To-Disk(STD): The tunLexl uf Lhe systerm is Illdirildiledl uri Lhi Naltaga is removed from the system agent domain disk. All of the power is shut down excep- power for the logic to resume The 54 and ss states are treated the same 12C SMB Address Soft-off: System context is not maintained. All nf the power is shit dowl ic to restart. A full boot is required to roster. A full PCB signal Impedence list boot is required when wakin ALC5640 The s4 and s5 states are treated te same Mcchanical OFF Systom content is not maintained. Al power shutdown except for LIe RTC. No Wake" veils die possible, because the syslelTl REAR CAMERA does not have any power. This state occurs if the user removes the a level that is insuff icient tc pawer the"waking"logic. when system power FRONT CAMERA returns, transition will depend on the sate just prior to the entry to G3 Table 121, g, s and C Statc Combinations G-SENSOR Global slee Processor Proces TOUCH PANEL (G)State(S)State State system Clocks Description (c)state PMIC C1/C1E AuJto-Halt Auto-halt 1.0mm Board stack up description DeeF Power Down Copper: 1/20 1 mil Trace Impedence: Microstrip Dual-Striplinp Stripline Down Copper: 104 1. 2m11 85p±12% Deep power Corc: 3.1496mi1 Down Copper: 10Z 1. 2mil 50±10%(3G)125ML A Cf except rtC internal Suspend to Disk er: 1OZ 1. 21 ring osc c。re:3.1496mi1 45Ω±10% 午线 Capper: 102 1. anil (OTHER) 4 MIL 4 MIL Power off f except rtc 8 internal PP:2. mil ring osc :Copper:1/2021.mil Power off Power ofh I lard off Total: 34.8992MIL PCB PLACEMENT(TOP REⅤIEW BYT Cold Boot sequence Parameter Description pical MaxUnits Signals from Soc TO il Ramp-Up Time from 10% to 0.08 VBAT VRTC 90% vo tage level BUCK3-V1PO55/V1POA V1POS Rail to Subsequent Rail Turn-On 0.7 ms BUCK6-V1P8 BUCKS- VNN FLDO2-VIP2AS T2 V3P3A valid to RSMRST B 50 ALDO3-v3P3A de-assertion RSMRST B T3 VREFDQ valid ( within +/-10% of50 70 SUSPWRDNACK its final normal value)to BUCK4- VDDQ DRAMPWROK assertion FLDO3- VREFDQ RSMRST B de-assertion 80 DRAMPWROK us BJCK1·VCC to slp sox B de-assertion DLDO1-eMMC SLP SOIX B de-assertion to first SLP SOTⅩB SX rail turn-on delay FLDO1-VIP2SX 〔 ore rails valid to VCCAPWEROK|8 ms BUCk2-V1POSX Vcc△ PWROK and CoREPWroK assertion COREPWROK T7 〔 assertion to6 PLTRST B pltrST B de-assertion Note The power on interval of each BUCK/LDo is 1 ms 午线 BYT SoC Initiated Cold Off Sequence Signals from Soc Parameter Descript Min Ma Units PLTRST B SLP SOIX B PLTRST-Bassertion to SLP-SOIX_B 31 assertion SUSPWRDNACK T1→ CORFPWROK SLPSⅨ b de-assertion to VCCAPWROK SUSPWRDNACK assertion Non default on LDOS SLPSⅨ b assert on to70 150 EUCK2-V1POSX VCCAPWROK and COREPWROK FLDO1-V1P2SxX 录↓-74 de-assertion DLDO1-eMMC 于T5 T3 VCCAPWROK and COREPWROK o ce-assertion to first vr starts to BUCK1-VcC turn off DRAMPWROK Rail Ramp-down Time from 90% FLDO3- VREFDQ to 10% voltage BUCK4-/DDo Rail to Subsequent Rail Turn-Off 0.7 RSMST B A』DO3.v3=3As 6 DRAMPWROK de-assertion to o 50 FLDO2-Y1F2A/S VREFDQ starts to turn off BUICK5-VNN T7 RSMRST B assertion to V3P3A 50 BUCK6-V1P8A starts to turn off BUCK3-V1P05AV1P15 午 BYT SoC Initiated global reset Signals from SoC BYT Standby Entrance Sequence PLTRST B Signals from SoC SLP SOIX B SLP SOX B SUSPWRDNACK BUCK2·V1Pa COREPWROK FLDO1-V1P2SX VCCAPWRCK BUCK3-V1PO5S/N1POA VSLEEP V1POS Non-default on iIs BUCK1-VCC BUCK 2-V1POSX BUCK5-VNN VSLEEP FLDO1-V1P2SX Figure 9-12 DLDC1-eMⅣC BUCK1 VCC Table 9-13 Parameter Description Min Typic M ax Units Figure 9-10 SLP SOIX B assertion to first SXo 300 Table 9-10 rail starts to turn off DescripTion ypical Max Units I ime that the SLP_SIx_B signal stays.1 Rail ramp-down T ime from 90% ms Time tor which rai ls stay down betore to 10% voltage level power up sequence begins Hail to Subsequent Hail lurn-Off 0./ 1.3 ms BYT Standby Exit Sequence Del Signals from Soc Parameter Description Min Typical Max Units SLP SOX B SLP_ SOIX_B dc-asscrtion to first 300 BUCk3-V1PO5S/V1POA VBOOT SX rail starts to turn on VSLEEP T1 Rail Ramp-Up Time from 10% to ms V1POS 产T FLDO1-V1P2SX 9o%6 votage level BUCk2-ViPOSX oV I FT2+ Rail to Subsequent Rail Turn-On07 VSLEFP VBOOT Delay BUCK5-VNN VBOOT Total SoX exit latency: from 6 ms BUCK1-VCC sLP soix b de-assertion to all VRs dIe within ils specified tolerance Figure 9-13 增加电的开关电路耳机接口换成的料增加一路电给把所有的换成有极性的料屏的背光电预留一路的电用 plMe 予午鹜

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