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详细说明：MIPI CSI2 Brdge芯片，转成LVDS信号，便于FPGA接收。否则MIPI信号线无法直接接入FPGAme。m
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MC20901
Table of contents
1 General Description
2 Key Features
3 Block Diagram…
111画
3. 1 Block Diagram
4 Parametrics
5566
4.1 Absolute Maximum Ratings
4.2 Recommended Operating conditions
4.3 DC Characteristics
7
4. 4 AC Characteristics
5 Package Information
5.1 TQLMP-48 Package
画面
9
5.2 Pin Description
5.3 Package Information
6 Application notes…
12
6. 1 Application Overview
2
6.2 D-PHY to FPGa Bridge Application
13
6.3 D-PHY to FPGA Bridge Application with Bus Turnaround
6. 4 Signal levels
15
6.4.1 HS-X-P and HS-X-N LVDS Outputs *)
15
6.4.2 LP-X-P and LP-X-N CMOS Outputs *)
15
6.4.3 DPHY-X-P and dPHY-X-n Inputs *
6.4.4 GPIO-0, GPIO-1, BTA, PINSWAP CMOS Inputs
15
6.5 Configuration Using gPlo-0 and GPio-1
15
66 Configuration Using BTA.……
15
6.7 Configuration Using PINSWAP
6.8 Input to output signal diagram
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7 Legal Disclaimer Notice
17
8 Contact Information
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Meticom gmbh
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MC20901
1 General Description
The MC20901 is a high performance 5 Channel FPGa bridge IC, which converts MIPI D-PHY
compliant input streams into LVDs high speed and Cmos low speed output data streams
The MC20901 can also convert an SLVs signal into an LVDs signal
The MC20901 outputs can be directly connected to FPGAs or DSPs
Data rates range from 0 Mbps to 2.5 Gbps in HS(High Speed)mode and up to 20 Mbps in LPDT (LOW
Power Data Transmission) mode
2 Key Features
Input is compliant to MIPI D-PHY interfaces using the DSl, csl-1 and csl-2 standards
o Hs mode data rate: up to 2.5 Gbps
o LPDT mode data rate: up to 20 Mbps
Conversion of slvs input to LVds output
o SLVS data rate: up to 2.5 Gbps
BtA (Bus Turnaround option for Channel A or E
Pin swap option(all channels simultaneously
5 Channel device(e. g. 4x DATA, 1X CLK)
D-PhY input termination automatically switched depending on hs or LP mode
No additional level shifters needed
Arbitrary power up sequence
Available as a bare die
o RoHS compliant, Pb-free
Available in a TQLMP-48 package
o 7mm *7mm*0.9mm
0.5mm pitch
o RoHS compliant, Pb-free
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MC20901
3 Block Diagram
3.1 Block Diagram
VDDIO
VDD
GND
D-PHY-E-P K
2HS-E-P
D-PHY-E-N KH
→HS-EN
CH-E
十
LP
CLP-E-P
BTA
E LP-E-N
D-PHY-D-P◆
CHS-D-P
Shifter
D-PHY-D-N◆
EHS-D-N
CH-D
Level
Shift
D-PHY-C-P
>HS-C-P
Shifte
D-PHY-C-N◆
ZHS-C-N
CH-C
CLP
LP-C-P
Shifter
A LP-C-N
D-PHY-B-P
>HS-B-P
Shifter
D-PHY-B-N◆
C HS-B-N
CH-B
LP-B-P
Shifter
>LP-B-N
D-PHY-A-P KH
HS-A-P
Shifter
D-PHY-A-NK
DHS-A-N
CH-A
丶LPAP
Level
BTA
Shifta
D LP-A-N
State machine
P| N SWAP◆
Figure 1: Functional Block Diagram of the MC20901
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MC20901
4 Parametrics
4.1 Absolute Maximum Ratings
Symbol
Parameter
Condition
M
Max Unit
Supply voltage
-0.5
3.6
Supply voltage
0.52.0
Storage temperature
55
125
C
Junction temperature
(HBM; 100 pF,
ESD
Electrostatic discharge voltage capability
2.0
KV
1.5k9)
VE
Electrostatic discharge voltage capability(HBM; 100 pF,
ESD-Dout
500
V
at differential l/Os
1.5kQ
Table 1: Absolute Maximum Ratings
to these values for extended periods may affect device reliability. If the device is operated beyond the range of Operatlosures
Absolute Maximum Ratings may not be exceeded to the device without causing permanent damage or degradation. Exp
Conditions functionality is not guaranteed
4.2 Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ Max Unit
DDIO
Supply voltage
2.3
2.5
2.7
Supply voltage
1.1
1.3
GND
Ground
0
Vnoise, dd Maximum allowed supply noise on VoD see Figure 2
100
Ambient temperature
-40
25
100
Table 2: Operating Conditions
DD
0
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