JEDEC standard No.21, DDR3 DIMM design spec204-Pin

文件名称: JEDEC standard No.21, DDR3 DIMM design spec

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详细说明：204-Pin DDR3 SDRAM Unbuffered SODIMM Design SpecificationJEDEC Standard No 21c Page42018-3 Decoupling Capacitor Guideline 28 Differential Clock Net structures 29 Clock Net Wiring CK[1: 0], CK[1: 0](Raw Cards A, c) 29 Clock Net Wiring CK[O], CK[O](Raw Card B) 30 Clock Net Wiring CK[1: 0], CK[1: 0](Raw Card D) 31 Clock Net Wiring CK[1: 0 ], CK[1: 0](Raw Card F) 33 Control Net Structures S[1: 0], CKE[1: 0], ODT[1: 0](Raw cards A, C) 35 Control Net Structures S [O], CKE[O], ODT[O](Raw card B) 35 Control Net Structures S [O], CKE[O], ODT[O](Raw card D) 36 Control Net Structures s[1: 0], CKE[1: 0], ODT[1: 0](Raw card F) 38 Address/Command Net Structures AX, BAx, RAS, CAS, WE(Raw cards a, B) 40 Address/Command Net Structures AX, BAX, RAS, CAS, WE(Raw card C) 41 Address/Command Net Structures AX, BAX, RAS, CAS, WE(Raw card D) 42 Address/Command Net Structures AX, BAX, RAS, CAS, WE(Raw card F) 45 Data net structures ..47 Net Structure Routing for DQ[63: 0], DM[7: 01, DQS[7: 01, DQS[7: 0](Raw card A, F) 47 Data Net Structures DQ[63: 01, DM[7: 0 DQS[7: 01, DQS[7: 0](Raw cards B, C) 49 Data Net Structures DQ[63: 0], DM[7: 01, DQS[7: 0], DQS[7: 0(Raw cards D)............51 Cross section Recommendations 52 Example 6 layers stack-up for Raw Card A, c 52 EXample 8 layers stackup for Raw Card B, D, F.. Test Points,… 55 Raw Card A Test Points 55 Raw Card B Test Points… 56 Raw Card c Test points Raw Card d Test Points 58 Raw Card f Test points .59 Serial Presence Detect Definition mmmmmmmm. 60 Serial Presence Detect Data Example 61 Product label SO-DIMM Mechanical Specifications…,,,,,,,.,,,,,,,…,…,65 Application Note RB IBIBER ARBIBIRIRBEBERBIABBIBBBRBBIRBIREBER BRBBBRBRBRBRROE ■口m国■■■■■m口■■■■■■■m■■■mD口■■■■■ 66 Max cin for the stacked dram on r/cd x8 2ranks module 66 Release 18A Revision 1.0 JEDEC Standard No 21C Page42018-4 1. Product Description This reference specification defines the electrical and mechanical requirements for the PC3-12800 memory module, a 204-pin, 800MHz clock(1600 MT/s data rate), 64-bit wide, Unbuffered Synchronous Double Data Rate 3(DDR3)DRAM Small outline dual In-Line Memory Module(DDR3 SDRAM SO-DIMMs ). It also defines a slower version, the PC3-10600, using 667MHz clock(1333 MT/s data rate)DDR3 SDRAMs, the PC3-8500 using 533MHz clock(1066 MT/s data rate)DDR3 SDRAMs, the PC3-6400, using 400MHz clock(800 MT/s data rate)DDR3 SDRAMs. These DDR3 SDRAM SO-DIMMs are intended for use as main memory when installed in systems such as mobile personal computers Note: R/C D(2ranks x8 stacked DRAM)is defined only for PC3-6400& PC3-8500 Reference design examples are included which provide an initial basis for Unbuffered So-DIMM designs. Any modifications to these reference designs must meet all system timing, signal integrity and thermal require ments for 800MHz clock rate support. Other designs are acceptable, and all Unbuffered DDR3 SO-DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the system Product Family Attributes Attribute Values Notes SO-DIMM Organization X64 Dimensions(nominal) 30.0 mm high 67.6 mm wide /Mo-268 variation CA So-DIMM Types Supported Unbuffered Pin Count 204 DDR3 SDRAMs Supported 512Mb. 1Gb 2Gb 4Gb Capacity 256MB.512MB.1G8.20B.4G8.8GB Serial Presence Detect Consistent with jEdEc latest revision 1.5VV Voltage Options Nomina 1.5VVoDQ 3.0V-36V VDD SPD Interface SSTL 15 Note 1: VDD SPD can not be tied to VoD or VoDQ on the DDR3 SO-DIMM Raw Cards Summary Raw Card Number of DDR3 SDRAMs SDRAM organiza- Number of Comments tion Ranks A 8 x16 2 Max DRAMWxL=12.3 x 20.0 B 8 8 Max DRAMWxL=12.3x 20.0 C X1 Max DRAMWXL=12.3x 20.0 Max DRAMWxL=123x200 16 x8 Stacked 2 Pc3-6400,85000nly Revision 1.0 Release 18A JEDEC Standard No 21c Page42018-5 E 16 8 for planar with square DRAM(Design on Hold) X8 Planar with rectangle DRAM, Max DRAMWXL=10.5×14. Release 18A Revision 1.0 JEDEC Standard No, 21C Page42018-6 2. Environmental Requirements DDR3 SDRAM Unbuffered So-DIMMs are intended for use in mobile computing environments that have lim ited capacity for heat dissipation Absolute Maximum Ratings Symbol Paramete Rating Units Notes TOPR Operating Temperature(ambient) 0ta65 oC STG Storage Temperature 50to100 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect re liability 3. Architecture Pin Description CK[10] Clock Inputs, positive line 2 DQ[63: 0] Data Input/Output CK[10] Clock inputs negative line DM[7: 0] Data Masks CKE[1: 0 Clock Enables DQS[7: 0] Data strobes RAS Row Address strobe DQS[7: 0] Data strobes complement 8 CAS Column Address strobe 1 RESEt Reset Pin WE Write enable TEST Logic Analyzer specific test pin(No connect on sO DIMM) s[1:0] Chip selects EVENT Temperature event pin A[9: 0 ], A11, A[15: 13] Address Inputs 14 Core and l/o Power 18 A10/AP Address Input/Autoprecharge Ground 52 A12/BC Address Input/Burst chop BA[20] SDRAM Bank Address REFDQ REFCa Input/Output Reference ODT[1:0] On-die termination control VDD SPD SPD and Temp sensor Power SCL Serial Presence Detect ( SPD)and Thermal sensor(TS)Clock Input 1 Vtt Termination voltage 2 SDA SPD and TS Data Input/Output Reserved for future use SA[10] SPD and Ts address Total: 204 Revision 1.0 Release 18A JEDEC Standard No 21c Page42018-7 Input/Output Functional Description Symbol Type Polarity Function CKO/CKO rOss The system clock inputs. All address and command lines are sampled on the cross point of the Input CK1/CK1 rising edge of CK and falling edge of CK. a Delay Locked Loop(DLL) circuit is driven from clock inputs and output timing for read operations is synchronized to the input clock CKE[1: 0] Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the self Refresh mode Enables the associated dDR3 SDRAM command decoder when low and disables the com- s[10] Input Active Low mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by so; Rank 1 is selected by $1 RAS. CAS WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS RAS, and we define the operation to be executed by the sdram BA[20] Input Selects which DDR3 SDRAM internal bank of eight is activated ODT[1: 0 Input Active High Asserts on-die termination for dQ dM, dQs, and dQs signals if enabled via the ddr3 SDRAM mode register During a Bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of cK. during a read or Write command cycle defines the column address when sampled at the cross point of the rising edge of CK and fall- A[9:0], ing edge of CK. In addition to the column address, AP is used to invoke autoprecharge opera A10/AP tion at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and A11 Input BAO-BAn defines the bank to be precharged If AP is low, autoprecharge is disabled. during a A12/BC Precharge command cycle, AP is used in conjunction with BAO-BAn to control which bank(s)to 15:1 precharge. If AP is high, all banks will be precharged regardless of the state of BAO-BAn inputs If AP is low, then BAO-ban are used to define which bank to precharge A12(BC)is sampled during READ and WRITE commands to determine if burst chop(on-the fly) will be performed (HIGH, no burst chop LOW, burst chopped DQ63:0] In/Out Data Input/Output pins The data write masks, associated with one data byte In Write mode, DM operates as a byte DM[7: 0] Input Active High mask by allowing input data to be written if it is low but blocks the write operation if it is high.In Read mode. DM lines have no effect The data strobes, associated with one data byte sourced with data transfers In Write mode DQSI7 the data strobe is sourced by the controller and is centered in the data window In Read mode In/Out Cross DQS[7 oint the data strobe is sourced by the ddr3 SdRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and dQs SPD Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the mod ule VREEDQ VREECA Supply Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the sPD EEPROM and Temp sen SDA In/Out sor. A resistor must be connected from the sda bus line to Vod sPd on the system planar to act as a pu‖up SCl Input This pin is used to clock data into and out of the sPd EEProm and Temp sensor. a resistor ust be connected from the SCL bus line to VdD SPd on the system planar to act as a pull up SA[1:] Input Address pins used to select the serial Presence detect and temp sensor base address TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory mod- ules (So-DIMMs) Release 18A Revision 1.0 JEDEC Standard No, 21C Page42018-8 Input/output Functional Description Symbol TypePolarity Function EVENT Wire- Active Low This pin is an output of the thermal sensor to indicate critical module temperature. a resistor OR Out must be connected from EVEnT bus line to VDdSPd on the system planar to act as a pullup RESET In Active Low This signal resets the DDR3 SDRAM Revision 1.0 Release 18A JEDEC Standard No 21c Page420.189 DDR3 SDRAM SO-DIMM Pinout Pin Front Pin Back Pin Front Pin Back Pin front Pin Back Pin front PinBack # Side Side# Side # Side Side Side side Side FDQ2 Vss53DQ1954Vss105 106 DD 157DQ42158DQ46 Vss 4DQ455ss56DQ28107A10AP108BA1159DQ43160DQ47 5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161 Vss162Vss DQ1 8 Vss59 DQ25 60 sS 111 112VDD1163DQ48164DQ52 9vs100as061vs62s311wE1430165D4916053 11 DMO 12 DQS063 DM3 64 DQS3115 CAS 116 ODTO167 Vss 168 Vss 13 Vss14 Vss65 Vss66Vss117 DD 118 169DQs6170DM6 15DQ216DQ667DQ2668DQ30119 A13 120 ODT1171 DQS6 172 Vss 17DQ318DQ769DQ2770DQ31121 S1 122 NC 173 Vss 174DQ54 19 Vss 20 Vss71 Vss 72 Vss 123 DD 124 v DD 175DQ50176DQ55 21 DQ8 22 DQ1273 CKEO 74 CKE1125 TEST 126 VREFCA177DQ5117 Vss 23DQ924DQ1375 76VDD127 Vss 128 Vss 179 Vss 180DQ60 25 Vss 26 V 77 NC 78A153129DQ32130DQ36181DQ56182DQ61 27DQS128DM179BA280A143131DQ33132DQ37183DQ57184Wss 29 DQS1 30 RESET 81 VDD 82 VI 133 VSS 134 Vss 185 Vss186 DQS7 31 Vss 32 Vss 83 A12/BC84 A11 135DQs4136DM4187DM7188DQs7 33DQ1034DQ14|85A9 A7 137DQs4138 Vss VSS 190 Vss 35DQ1136DQ1587VD88VoD139Vss140DQ38191DQ58192DQ62 37 Vss 38 Vss89 A890 A6 141DQ34142DQ39193DQ59194DQ63 39DQ1640DQ2091A592 143 DQ35 144 Vss 195 Vss 196 Vss 41DQ1742DQ2193Vp 94 145 Vss 146 DQ44197 SA0198 EVENT 43 Vss 44 VSs 95 A3 96 A2 147 DQ40 148 DQ45 199 VDDSPD 200 SDA 45DQS246DM297A1 98 AO 149DQ41 150 Vss 201 SA1 202 SCL 47 DQS2 48 Vss 99 DD 100V 151 Vss 152DQs5203 Vtt 204 Vt 49Vss50DQ22101cK0102cK1 153 DM 154 DQS5 511DQ1852DQ23103cK0104cK1155Vss 156 Vss 1. NC= No Connect. nu= Not Useable, RFU= Reserved Future Use 2. TEST(pin 125)is reserved for bus analysis probes and is nc on normal memory modules 3. This address might be connected to nc balls of the DRAMs(depending on density); either way they will be connected to the term nation resistor Release 18A Revision 1.0 JEDEC Standard No 21C Page42018-10 Block Diagram: Raw Card Version A(Populated as 2ranks of x16 SDRAMs 图目 SCL- SCL AC Temp Sensor SA EVENT The spd may be integrated with the Temp EVENT DSO LDQS LDQS 240ohm a separate coinponleilL SCL SCL DMO LDM ZQ LDM ZQ- SAO DQ[07 DQ 10.71 DQ [C:7 C (SPD SDA UDQS DO LIDQS D4 SAl DOS UDOS UDOS UDM DQ[8:15] DQ[8:1 DQ[8:1 图e§引|图影§ VInSPD VREECA VREFDO DQS2 240ohm LDOS 240ohm DO-D7 DOS LDOS +/-1% DO-D7, SPD, Temp sensor DM2 LDM CKO D0-D3 DQ[623] M DQ 10: 7 DQ[C: 7] UDQS D5 CKI UDQS UDOS DM3 UDM CKI D4-D7 DQ|2431 DQ[8:1 DQ[8:1 EVENT 图图影|图影到 ESET D0=D7 DOS4 LDOS 240oh DOS4 LDQS +/-1% LDQS ZQ-W D4 DM4 LDM DQ[3239] Q[0:7 LDQS D2 UDQS D6 CDO DMS CDM UDM DQ[4(47] DQ[8:1习 DQ[8:15 比|8 叫!DoV D2V4 D3 He DQS6 240oh 2495 zQ√ LDM DQ[4855 DQ[0:7 DQ[07 Address and Control lines LDQS D3 UDQS D7 DM7 UDM DQwiring may differ from that shown DQ[S663] 8:1习 DQ[8:1 however, DQ, DM, DQs and dO elations hips are maintained as shown 送比|图 IRank O Rank 1 区AB贪 Wh E Revision 1.0 Release 18A

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