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详细说明:micron nand flash MT29F1G08ABAFA 1024 blocks, 8bit ecc.Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Features
Contents
Important Notes and Warnings……………,…,…,…,…,…,……,…,…,…,…,…,………………
General Description......,.....,..,.....,..,,,,…
Signal Descriptions ........
Signal Assignments…….………
∴11
Package Dimensions……,…,…,…,…,…,…,,…
Architecture∴.
15
Device and array organization
16
Asynchronous Interface Bus Opcration
D看番
·;·····
Asynchronous Enable/Standby .......................................................... 17
Asynchronous Commands
17
Asynchronous Addresses
19
Asynchronous Data Input……,….,….,.,,,…
20
Asynchronous Data Output...
21
Write protect#
22
Ready/ busy#
…………………2
2
Device initialization
26
Power Cycle requirements…,,,,…,,…,,,,,,
27
Command Definitions…
非4音
28
Reset operations…,…,…,…,…,…,…,…,…,…,…,,…,30
RESET (FFh)
30
Identification Operations
,31
READ ID90h)…….31
READ ID Parameter tables
32
READ PARAMETER PAGE ECh
34
Parameter Page Data Structure Tables
·非垂
35
READ UNIQUE ID (EDh).............
37
Feature Operations∴,…,,,…,,…,,…,,…,…,,,,,,…,,,38
SET FEATURES(EFh)…….38
GET FEATURES (EEh)
·D垂
39
Status Operations
42
READ STATUS (70h)
看D·垂
43
READ STATUS ENHANCED
..:··
43
Column Address operations
45
RANDOM DATA READ (05h-EOh)..........................................
RANDOM DATA INPUT (85h)
46
PROGRAM FOR INTERNAL, DATA INPUT (85h)..............
47
Read operations
48
READ MODE(00h)∴.,49
READ PAGE (00h-30h).................................................................49
READ PAGE CACHE SEQUENTIAL (31h)
··
50
READ PAGE CACHE RANDOM(00h-3lh)………,50
READ PAGE CACHE LAST (3Fh
,·垂
51
Program Operations
53
PROGRAM PAGE (80h-10h
53
PROGRAM PAGE CACHE (80h-15h)
54
Erase operations
56
ERASE BLOCK (6Oh-DOh)
56
Internal Data Move Operations…,…,…,…,,
着垂垂·垂
57
READ FOR INTERNAL DATA MOVE (00h-35h
57
PROGRAM FOR INTERNAL DATA MOVE (85h-10h)
着番
∴58
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Features
Block lock feature
WP# and block lock
60
UNLOCK(23h-24h)……
60
LOCK(2Ah)∴
62
LOCK TIGHT(2Ch)...................
63
BLOCK LOCK READ STATUS(7Ah).…………64
PROTECT Command
65
PROTECtION Command details
,66
One- Time Programmable(OTP) Operations……,,…,…,…,
Legacy OTP Commands………
67
OTP DATA PROGRAM (80h-10h)........
67
RANDOM DATA INPUT(85h)……….68
OTP DATA PROTECT(80h-10
69
OTP DATA READ(00h-3oh)……
70
ECC Protcction.………………………………
72
Error Management……,
D
······
74
Electrical Specifications
75
Electrical Specifications- DC Characteristics and Operating Conditions…………………
77
Electrical Specifications- AC Characteristics and Operating Conditions………,…,…
79
Electrical Specifications- Program/Erase Characteristics
82
Asynchronous Interface Timing Diagrams………
83
Revision historγ…
看·着4·垂
∴.93
Rev.E-6/19
垂音,音垂垂
93
Rev.D-3/19.93
Rev.C-1/19
93
Rev.B-5/18.
93
Rev.A-2/16
93
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Features
List of Figures
Figure 1: Marketing Part Number Chart
Figure 2:48- Pin tsop-ypel,CPL(IopⅤiew)……,,…,…,,…,…,…,,…
Figure 3: 6-Ball VFBGA, X8(Balls Down, Top View)
12
Figure4:48- Pin tsop-Iype1,CPL(WP)…………
Figure5:63- BallvFbga(H4)9 mmxllmn………,…,…,…,……,……,…………,14
Figure6: NAND Flash Die (lun) Functional Block diagram……..…,….,…,…,,…
15
Figure 7: Array organization
Figure8: Asynchronous Command Latch Cycle………………………………………………,18
Figure 9: Asynchronous Address latch Cycle
19
Figure 10: Asynchronous Data Input Cycles...........
20
Figure 11: Asynchronous Data Output Cycles…………,……
21
Figure12: Asynchronous Data Output Cycles( EDO Mode)……,…,
22
Figure 13: READ/BUSY# Open Drain
23
Figure I4:" Fall and"Rise(③3.3VVcc)∴……,…,…,…,…,,…,…,……,,…,…
24
igure15: LOL VS.Rp(VvCC=3.3VVco)……,…,…,…,…,…,,…………,,24
Figure 16: Tc VS R1
25
Figure l7:R/B# Power- On behavior…………………………,26
Figure18: RESET(rh) Operation……
∴30
Figure 19: READ ID (90h) with 00h Address Operation .................................. 31
Figure 20: READ ID(90h)with 20h Address Operation
31
Figure 21: READ PARAMETER (ECh)Operation
34
Figure22: READ UNIQUE ID(EDh) Operation………,…,,…,…,…,…,,…,,……,37
Figure 23: SET FEATURES (EFh) Operation
39
Figure 24: GET FEATURES (EEh)Operation
∴39
Figure 25: READ STATUS(70h)Operation
·非垂
43
Figure26: READ STATUS ENHANCED(78h) Operation………….…,…..,…...….,.,…,…..,4
Figure27: RANDOM DATA READ(05h-loh) Operation…………
···.········.···
Figure 29: PROGRAM FOR INTERNAL DATA INPUT(85h)Operation
Figure28: RANDOM DATA INPUT(85h) Operation….……
46
·D垂
47
Figure 30: READ PAGE (0Oh-30h)Operation
49
Figure3l: READ PAGE(00h-30h) Operation with Internal ECC Enabled……………………………,50
Figure 3 2: READ PAGE CACHE SEQUENTIAL (3lh)Operation...................
..:··
50
Figure 33: READ PAGE CACHE RANDOM (00h-31h)Operation
51
Figure34: READ PAGE CACHE LAST(3Fh) Operation…………,…,…,……
52
Figure 35: PROGRAM PAGE(80h-10h)Operation
54
Figure 36: PROGRAM PAGE CAChe(80h-15h)Operation (Start)
55
Figure 37: PROGRAM PAGE CACHE (80h-15h)Operation (End)
55
Figure38: ERASE BLOCK(60h-D0h) Operation……………………,…,…,…,…,,…,,,,,…,…,56
Figure 39: READ FOR INTERNAL DATA MOVE (00h-35h)Operation......................... 57
Figure 40: READ FOR INTERNAL DATA MOVE(00h-35h)with RANDOM DATA READ(05h-EOh)........58
Figure 42: INTERNAL DATA MOVE (85h-10h)with RANDOM DATA INPUT with Internal ECC Enabled ...........58
Figure 41: INTERNAL DATA MOVE (85h-10h)with Intcrnal ECC Enabled
∴58
Figure 43: PROGRAM FOR INTERNAL DATA MOVE(85h-10h)Operation
···:·:····
.59
Figure 44: PROGRAM FOR INTERNAL DATA MOVE (85h-10h)with RANDOM DATA INPUT(85h)
59
igure 45: Flash array Protected: Invert Area Bit=0
看看·.音垂看垂·,垂非·垂
61
Figure 46: Flash Array Protected: Invert Area Bit= 1
61
Figure 47: UNLOCK Operation
垂,·垂
6
Figure48;: LOCK Operation.…,,,…,,,…
着垂垂·垂
62
Figure 49: LOCKTIGHT Operation
63
Figure 50: PROGRAM/ERASE Issued to Locked block
着番
63
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Features
Figure51: BLOCK LOCK READ STATUS……
6
Figure52: BLOCK LOCK Flowchart…,…,…
65
Figure53: Address and Command Cycles……,…,,
66
Figure54: OTP DATA PROGRAM( After Entering OTP Operation Mode)…………,…,…,…,…,…,…,68
Figurc 55: OTP DATA PROGRAM Opcration with RANDOM DATA INPUT(Aftcr Entering OTP Opcration Modc)69
Figure 56: OTP DATA PROTECT Operation(After Entering OTP Protect Mode)..............70
Figure 57: OTP DATA READ
71
Figure58: OTP DATA READ with RANdOM DATA READ Operation…………,71
Figure59: RESET Operation…,…,…,…,……,
83
Figure 60: READ STATUS Cycle
··
83
Figure61: READ STATUS ENHANCED Cycle…………
84
Figure 62: READ PARAMETER PAGE
.:······:·.··:·.····
84
Figure63: READ PAGE∴.…….…...….….…..….……..…………………………85
Figure 64: READ PAGE Operation with CE#"Don't Care
86
Figure 65: RANDOM DATA READ
看4音;垂垂
86
Figure 66: READ PAGE CACHE SEQUENTIAL
87
Figure 67: READ PAGE CACHE RANDOM
88
Figure 68: READ ID Operation
89
Figure69: PROGRAM PAGE Operation..…,,…,
89
Figure70: PROGRAM PAGE Operation with CE#“Don' t Care”…
90
Figure 71: PROGRAM PAGE Operation with RANDOM DATA INPUT
90
Figure 72: PROGRAM PAGE CACHE
·看
..91
Figure 73: PROGRAM PAGE CACHE Ending on 15h
91
Figure74: INTERNAL DATA MOVE∴…………
·垂4看D垂看
92
igure75: ERASE BLOCK Operation.………,…,…,……,………,92
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Features
List of tables
Table 1: Signal Definitions
音看
10
Table2: Array Addressing∴…,,…,,…,…,…,…,…,…,…,…,…,…,…,,…,……,…,16
Table 3: Asynchronous Interface Mode selection
Table 4: Power Cycle requirements
27
Table 5: Command set
4垂
.28
Table 6: REAd ID Parameters for Address ooh
32
Table 7: READ ID Parameters for address 20h
32
Table8: Parametcr Page Data Structure…………
35
Table 9 Feature Address definitions
38
Table10: Feature address9oh- Array Operation Mode………
38
Table 1l: Feature Addresses olh: Timing mode………………,…
39
Table 12: Feature Addresses 80h: Programmable I/O Drive Strength
41
Table 13: Feature Addresses 8]h: Programmable r/B# Pull-Down Strength
41
Table 14: Status Register Definition…………
42
Table 15: Block Lock Address Cycle Assignments
··;···.··
61
Table 16: Block lock Status register Bit Definitions
..:·....:.
64
Table 17: Spare Area mapping(x8B)……
Table 18: ECC Status∴
Table 1s9; Error Management details.……………………………,74
Table 20: Absolute Maximum Ratings
Table 21: Recommended Operating Conditions
·······;·····
Table22: Valid blocks…,,……,,,…,,,,,…,…,
555
Table 23: Capacitance.......
··:
.76
Table 24: Test conditions
Table25: DC Characteristics and Operating Conditions(33V)……,…,…
77
Table26: DC Characteristics and Operating Conditions(1.8V)……….….………………78
Table27:AC( haracteristics: Command,Data, and Address Input(3.3V)……………79
Table28: AC Characteristics: Command,Data, and Address Input(1.8V)……………
Table 29: AC Characteristics: Normal Operation (3.3V)
音垂音
80
Table 30: AC Characteristics: Normal Operation(1.8v)
.80
Table 31: Program/Erase Characteristics
82
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc (Micron")reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by micron
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/ distrib
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs,damages, and expenses and reasonable attorneys'fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use ofnon
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con
ditions of sale between customer/distributor and any customer of distributor /customer (1) state that micron
products are not designed or intended for use in automotive applications unless specifically designated by micron
as automotive-grade by their respective data sheets and (2)require such customer of distributor/customer to in
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications
Critical Applications. Products are not authorized for use in applications in which failure of the micron compo-
nent could result, directly or indirectly in death, personalinjury, or severe property or environmental damage
(Critical Applications"). Customer must protect against death, personal injury, and severe property and environ
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims
costs, damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product
Customer Responsibility. Customers arc responsible for thc dcsign, manufacture, and opcration of thcir systcms,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMERS SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER S SYSTEM, APPLICATION OR
PRODUCT. Customers must ensure that adequate design, manufacturing and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en
vironmental damages will result from failure of any semiconductor component
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges )whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by micron's dul
authorized representative
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
General Description
General descripti。n
Micron NAnd Flash devices include an asynchronous data interface for high-perform
ance I/O operations. These devices use a highly multiplexed 8-bit bus(l/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and rE. Additional signals control
hardware write protection and monitor device status(r/B#
This hardware interface creates a low pin-count device with a standard pinout that re
mains the samc from onc density to anothcr, enabling future upgrades to higher densi
ties with no board redesign
a target is the unit of memory accessed by a chip enable signal. a target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the onFi specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization
CCMTD-1725822587-10323
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
Micron Confidential and Proprietary
ccr。n
1Gb: x8 NAND Flash Memory
Signal Descriptions
Signal Descriptions
Table 1: Signal Definitions
Signal?
Type Description
ALE
Input Address latch enable: Loads an address from l /O[7: 0] into the address register.
CE#
Input Chip enable: Enables or disables one or more die(LUNs)in a target
CLE
I Input command latch enable Loads a command from /0[7 into the command register.
LOCK
Input
When LOCK is HIGH during power-up the block lock function is enabled To disable the
BLOCK LOCK, connect LoCK to Vss during power-up, or leave it disconnected(interna
pull-down)
RE#
Input Read enable: Transfers serial data from the NANd Flash to the host system
WE#
Input Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash
WP#
Input Write protect: Enables or disables array PROGRAM and ERASE operations
O[15:0](x16
O
Data inputs/outputs: The bidirectional l/Os transfer address, data, and command infor-
atior
R/B#
OutputReady/busy: An open-drain, active-low output that requires an external pull-up resistor.
This signal indicates target array activity
Supply Vcc: Power supply
SupplyVss: Ground connection
NO
No connect: NCs are not internally connected. They can be driven or left unconnected
DNU
Do not use: DNUs must be left unconnected
Notes: 1. See Device and Array Organization for detailed signal connections
2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal
descriptions
CCMTD-1725822587-10323
10
Micron Technology Inc reserves the right to change products or specifications without notice
2016 Micron Technology, Inc. All rights reserved
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