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详细说明：imx8qxp datahsheet, This data sheet contains specifications for the i.MX 8QuadXPlus and 8DualXPlus processors, which, along with the i.MX 8DualX processor, comprise the i.MX 8X Family (for i.MX 8DualX specifications, see i.MX 8DualX Automotive and Infotainment Processors [IMX8DXAEC]). The i.MX 8X processors consist of three to five ARM®cores (two to four ARM Cortex®-A35 and one Cortex-M4F). All devices include separate GPU and VPU subsystems as well as a failover-ready display controller. Advanced multicore audio processing is supported by the ARM cores and a high performance Tensilica® HiFi 4 DSP for pre- and post-audio processing as well as voice recognition. The i.MX 8X Family supports up to three displays with multiple display output options, including parallel, MIPI-DSI, and LVDS. Memory interfaces for this deviceIntroduction Table 1.iMX 8QuadXPlus/8 DualXPlus advanced features(continued) Function Feature Memory 32-bit LPdDR4 1200 MHz 40-bit DDR3L933 MHZ(ECC option 1x Quad sPi which can be used to connect to an fPga 2x Quad SPI or 1x Octal SPI (FlexSPl) for fast boot from SPI NOR flash Jess SD 3.0 card interfaces( note: if eMMC is used, then 1x SD 3.0 available in IOMUX 1x eMMC5. 1/SD3.0(note: use of eMMC will restrict SD card availability to 1X SD3.0 due to IOMUX restrictions) RAW NAND (62-bit ECC support via BCH-62 module Display Controller Supports up to 3 independent displays(2x MiPl or LVDS+ 1x Parallel) Up to 1 8-layer composition Complementary 2D blitting engines and online warping functionality Integrated Failover Path Safe Assure)to ensure display content stays valid even in event of a software failure Display v/o TWO MIP1-DSI/LVDS Combo PHYs(each up to 1080p60 Each single phy can either be a 4-lane mipl-DSi or a 4-lane channel lvds interface for a total of 2 display interfaces. In combination, the two PhYs can be configured to be a single dual-channel LVDS interface x24-bit parallel LCD up to 720p60 (DDR bandwidth might limit the available resolution Camera l/o and video 1×MP|-Cs|with4-anes 1x8-bit/10-bit parallel csI Securi Enhanced High Assurance Boot (HAB) secure encrypted boot Random Number Generator with a high-quality entropy source generator and Hash_ DRBG(based on hash functions RSa up to 4096, Elliptic Curve up to 1023 AEs-128/192/256,DES,3DES.MD5,SHA-1,SHA224/256/384512 Dedicated Security Controller for Flashless ShE and HSM support, Trustzone, RTIC Built-in ECdSA/DSa protocol support 10x tamper pins (up to 5 active or 10 passive) Voltage and Temperature tamper detection 64 kB Secure RAM (can be erased via tamper detection) System Control System Control Unit (SCU) Power control. clocks reset Boot roms PMIC interface Resource domain controller i MX 8QuadXPlus and 8 dualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018 NⅩ P Semiconductors PRELIMINARY Introduction Table 1.iMX 8QuadXPlus/8 DualXPlus advanced features(continued) Function Feature 1x PCle 3.0(1-lane)with L1 substate support 1x USBOTG 3.0 with phy--USB 3.0 can be used as usB 2.0 1× USBOTG2.0( with Phy 2x 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB) 3X CAN/CAN-FD 1x Media Local Bus(MLB25/50) 6X UARTS 4x UARTs(3x with hardware flow control 1x UART tightly coupled with Cortex-M4F cores 1x SCU UART(Note: SCU UART is dedicated to the sCU and not available for general use 10x lc(note that there are two types of IC: High-speed I-C ports with DMA support and low-speed 12C ports with no DMA support, which are used in conjunction with a specific PHY interface-for example, for touchscreen) 4x 12C: High Speed, DMA support 4x 12C: LoW Speed, no DMA support 1x 12C: PMIc control (dedicated) 1x 12C: Cortex M4 F(dedicated) Note: 12C ports associated with a PhY(e.g MIPI DSI)can be used generally but require the phY to be powered on even if the Phy interface itself is not used 4X SAI (SAIO and SAl1 are transmit/receive SAl2 and SAl3 are receive only) 1x Enhanced Serial Audio Interface(ESAl 2X ASRC (Asynchronous Sample Rate Converter)(note: no lo signals are directly connected to this module) 1×SPDF( Tx and rx) 1x 6-channel ADC converter 3.3 V/1.8V GPIO 4x PWM channels 1x6×8KPP( Key Pad Port 1x MQS(Medium Quality Sound) 4X SP Packaging Case FCPBGA 21 x 21 mm, 0.8 mm pitch Case FCPBGA 17 X 17 mm, 0.8 mm pitch 1. MX 8QuadXPlus and 8 DualXPlus automotive and Infotainment Applications Processors, Rev. 0, 11/2018 PRELIMINARY NXP Semiconductors Architectural overview 1.1 Ordering Information ThesepartsarestillinpreproductionFormoreinformationcontactanNxprepresentativeatnxp.com 2 Architectural overview The following subsections provide an architectural overview of the i mX 8QuadXPlus/lDualXPlus processor system. L MX BQuadXPlus and 8 dualXPlus automotive and Infotainment Applications Processors, Rev. 0, 11/2018 NⅩ P Semiconductors PRELIMINARY 5 Architectural overvie 2.1 Block Diagram The following figure shows the functional modules in the processor system 区xUAR[X2区GP Memories x Quad SPI Iser CM4 Complex CPU Platform 1x Octal SPl 2x FlexSPI NOR Flash M4 Platform 4ⅹ ARM Cortex-A35 M4 CPU NAND CTRL (BCH62) RAW NEON VEP ONFI 3.2 NAND Flash MNCAU 32KB I$ 32KB D$ 1x eMMC 32-bit LPDDR SD 3 16KB codes 16KB systems 512KB L2 W/ ECC DDR 1200MHz 2X SD3.0 256KB TCM W/ ECC Trustzone PGHBN ntroller (UHS-D) 40-bit ddr3L PWM 933 MHZ 10/100/1000M -PUART LPI2C RGPIO 2x MU Internal m [Bu High Speed / 1x USB 3.0 OCRAM(256KB) 圆 1 pcle 3.0 Connectivity (1 lane) 1× USBOTG2.0 USB3 2x sdH oTG Phy MLB 2x USB2 2X ENE Imaging MLB/ MOST MJPEGMJPEG 24-bit parallel 25/50+DTCP Low Speed 1/0 and Timers DEC ENC IST I/F 4×4 Keypad 4X PWM 8x GPIO 2c 1xI2C 32-bit gPio 5X GPT KPP 2X WDOG Display Controller PI/LVI 12C W/DMA MIPI-DSI DMA and Shared Peripherals UART(5Mb/s)↓ LPI2C 1x I2d 2 x eDMA‖4 X LPUART4× LPSPI DPU CAN/CAN-FD 1x MIPI MIPI-CSI2 3x FlexCAN 4x LPI2C 1X ADC ADC (6 inputs) CSI2 4-lanes) Graphics Processing Ur System Control Unit GPU OMUX Parallel 8/10-bit SCU CM4 Complex I/F Parallel camera Debug Clock, Reset M4 Platform Video Processing Unit M4 CPU Boot Rom ower Mgmt Audio PMIC I/FLempmon MMCAU M CM 2X ASRC Security DSP Core 16KB code$16KB systems HIFI4 DSP SPDIF PDLF TX/RX 256KB TCM W/ECC 24M and 32k 32KB IS 18KB DS ESAI 小 ESAI TX/RX XTALOSC OTP SECO 512KB SRAM Sources T INTS WDOG P ADM(CM0+) 61KB TCM MQS HMQS L/R LPUART PI2C RGPIO 2X№U CAA 4ⅹSAI SAI TX/RX Mult-format decode 4 shaders 区xUAR区xL2g区xGPo JTAG H 265 Dec(4k30 Vulkan, OGLeS 3. 1 H264Dec(1080p60)ocL1.2,VG11 Detection ECC, RS 264Enc(108Cp30) 2D Blit Engine Secure RTc 54k Secure RAM Figure 1. i MX 8QuadXPlus/8 DualXPlus System Block Diagram 1. MX 8QuadXPlus and 8 DualXPlus automotive and Infotainment Applications Processors, Rev. 0, 11/2018 PRELIMINARY NXP Semiconductors Modules list 3 Modules list The i MX &QuadXPlus/&DualXPlus processors contain a variety of digital and analog modules. This table describes the processor modules in alphabetical order Table 2.i MX 8QuadXPlus/8DualXPlus modules list Block Block Name Brief Description Mnemonic ADC Analog- to-Digital The analog-to-digital converter(ADC)is a successive approximation ADC Converter designed for operation within an SoC APBH-DMA NAND Flash and BCH The AHB-to-APBH bridge provides the chip with a peripheral attachment bus ECC DMA Controller running on the AHB's HCLK, Which includes the AHB-to-APB PlO bridge for a memory-mapped o to the aPB devices, as well as a central dMa facility for devices on this bus and a vectored interrupt controller for the arm core A35 ARM(CPU1 2-4x Cortex-A35 CPUs with a 32KB L 1 instruction cache and a 32 KB data cache The CPUs share a 512 KB L2 cache ASRC Asynchronous Sample The Asynchronous Sample Rate Converter(ASRC)converts the sampling rate of Rate Converter a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs BCH-62 Binary-BCH ECC The bCH62 module provides up to 62-bit ECC for NAND Flash controller(GPM2 Processor CAAM Cryptographic CAAM is a cryptographic accelerator and assurance module CAAM implements Accelerator and several encryption and hashing functions, a run-time integrity checker, and a Assurance module Pseudo Random number generator(PrNG) CAAM also implements a Secure Memory mechanism In this device the security memory provided is 64 KB CSU Central Security Unit The Central Security Unit(CSU)is responsible for setting comprehensive security policy within the i MX 8 Family platform. The Security Control Registers(SCR)of the CSU are set during boot time by the haB and are locked to prevent further writing CTI Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is used by features of the coresight infrastructure CTM Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs DAP Debug Access Port The DAP provides real-time access for the debugger without halting the core to System memory and peripheral registers All debug configuration registers The daP also provides debugger access to JTAG scan chains Display controller Dual display controller DDR Controller DRAM Controller.Memory types: LPDDR4(no ECC)and DDR3L (ECC option) e channel of 32-bit memory · LPDDR4upto1.2GHz DDR3L up to 933MHz i MX BQuadXPlus and 8 DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018 NⅩ P Semiconductors PRELIMINARY Mo odules list Table 2. i MX 8QuadXPlus/8 DualXPlus modules list(continued) Block Block Name Mnemonic Brief Description DPR Display /Prefetch/ The dPR prefetches data from memory and converts the data to raster format for Resolve display output. Raster source buffers can also be prefetched unconverted. The resolve process supports graphics and video formatted tile frame buffers and converts them to raster format. Embedded display memory is used as temporary storage for data which is sourced by the display controller to drive the display DTCP Digital Transport Provides encryption function according to Digital Transmission Content Protection Content Protection standard for traffic over mlB25 /50 eDMA Enhanced direct 4x eDMA with a total of 96 channels (note: all channels are not assigned; see Memory Access the product reference manual for more information ·2× instances with32 channels each ·2× instances with16 channels each Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes Internal data buffer, used as temporary storage to support 64-byte burst transfers, one outstanding transaction per dma controller Transfer control descriptor organized to support two-deep, nested transfer operations Channel service request via one of three methods Explicit software initi Initiation via a channel-to-channel linking mechanism for continuous transfers Peripheral-paced hardware requests( one per channel) Support for fixed- priority and round-robin channel arbitration Channel completion reported via interrupt requests Support for scatter/gather DMA processing Support for complex data structures via transfer descriptors Support to cancel transters via software or hardware Each eDMA instance can be uniquely assigned to a difterent resource domain security(tz state, and virtual machine In scatter-gather mode, each transfer descriptor's buffers can be assigned to different smmu translation ENET Ethernet controller 2X 1 Gbps Ethernet AVB(Audio video Bridging IEEE 802. 1Qav ESAL Enhanced Serial Audio The Enhanced Serial Audio Interface(ESAI)provides a full-duplex serial port for Interface serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The esal consists of independent transmitter and receiver sections, each section with its own clock generator all serial transfers are synchronized to a clock. Additiona synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is also intended for periodic transters; however, it supports up to 32 words (time slots)per period. This mode can be used to build time division multiplexed (TDm)networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available The esal has 12 pins for data and clocking connection to external devices FIM FlexTimer Provides input signal capture and pwm support FlexCAN Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate(CAN FD) Network protocol and the can protocol according to the can 2. 0B protocol specification 1. MX 8QuadXPlus and 8 DualXPlus automotive and Infotainment Applications Processors, Rev. 0, 11/2018 PRELIMINARY NXP Semiconductors Modules list Table 2. i MX 8QuadXPlus/8 DualXPlus modules list(continued) Block Block Name Mnemonic Brief Description FlexSpi(Quad Flexible Serial Flexible sequence engine to support various flash vendor devices, including SPl/Octal SPl) Peripheral Interface lyper BusM devices Support for FPga interface Single, dual, quad, and octal mode of operation DDR/DTR mode wherein the data is generated on every edge of the serial flash Support for flash data strobe signal for data sampling in ddr and sdr mode Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one(virtuall)flash memory with doubled readout bandwidth GIC Generic Interrupt The giC-500 handles all interrupts from the various subsystems and is ready for Controlle virtualization GPIO General Purpose I/ Used for general purpose input/output to external devices. Each GPIO module Modules supports 32 bits of I/O GPMI General Purpose Media The GPMI module supports up to 8X NAND devices. 62-bit ECC( BCH)for NAND Interface Flash controller(GPMI). The GPMI supports separate DMA channels per NAND device GPT General Purpose Timer Each GPT is a 32-bit"free-running" or"set and forget"mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse When the timer is configured to operate in"set and forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison This timer can be configured to run either on an external clock or on an internal clock GPU Graphics Processing 1x GC7000Lite with 4x Vec4 shader cores(16 execution units HiFi 4 DSP Audio processor A highly optimized audio processor geared for efficient execution of audio and voice codecs and pre- and post-processing modules to offload the ARM core 12C Interface l-C provides serial interface for external devices lEE Supports direct encryption and decryption of Flex SPI memory type Provides decryption services (lower performance)for DRAM traffic Supports lo direct encrypted storage and retrieval Support for a number of cryptographic standards: 128/256-bit AES Encryption(AES-CTR, AES-XTS mode options Multiple keys supported Loaded via secure key channel from security block Key selection is per access and based on source of transaction OMUX OMUX Control This module enables flexible I/O multiplexing Each v/o pad has default and several alternate functions. The alternate functions are software configurable JPEG/dec MJPEG engine for Provides up to 4-stream decoding in parallel ecode JPEG/enc MJPEG engine for Provides up to 4-stream encoding in parallel encode i MX 8QuadXPlus and 8 dualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018 NⅩ P Semiconductors PRELIMINARY 9 Mo odules list Table 2. i MX 8QuadXPlus/8 DualXPlus modules list(continued) Block Block Name Mnemonic Brief Description KPP Key pad port he Keypad Port (Kpp)is a 16-bit peripheral that can be used as a 4 x 4 keypad matrix interface or as general purpose input/output(vO) PIT-1 Low-Power Periodic Each LPIT is a 32-bit "set and forget"timer that starts counting after the Lpit is PIT-2 Interrupt Timer enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the LPSPI0-3 Configurable SPl Full-duplex enhanced Synchronous Serial Interface. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals M4F ARM(CPU3 Cortex- M4F core AHB LMEM ( Local Memory Controller)including controllers for TCM and cache memores 256 KB tightly coupled memory (TCM)(128 KB TCMU, 128 KB TCML 16 KB Code bus cache °16 KB System Bus Cache ECC for TCM memories and parity for code and system caches Integrated Nested Vector Interrupt Controller(NvIc) Wakeup Interrupt Controller (WIC Floating Point Core MPU (Memory Protection Unit Support for exclusive access on the system bus MCAU (Crypto Acceleration Ur MCM(Miscellaneous Control Module) MIPI CSI-2 MIPI CSl-2 Interface The MIPI CSl-2 IP provides MIPl CSl-2 standard camera interface ports. The MIPI CSl-2 interface supports up to 1.5 Gbps for up to 4 data lanes MIPl-DSW/LVDS MIPI DS//LVDS Combo The MIPI DSI IP provides DSI standard display serial interface with 4 data lines interface The DsI interface supports 80 Mbps to 1.05 Gbps speed per data lane The Lvds is a high-performance 2-channel serializer that interfaces with LVDS displays Note: This is a combination PHY interface. It includes the digital logic and physical interface pins for both MiPl DSl (4 data lanes)and LvDs (4 differential pairs plus one for clock ). the interface can be pinned out either as mipi dsi or as Lvds However, it does not allow for simultaneous use on one interface MOSTO Media oriented Media local bus interface module that provides a link to a mosto data network Systems Transport using the standardized MedialB protocol Supports 3-wire interface(MLB25 MLB50) MQS Medium Quality Sound Medium Quality Sound(MQS)is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins OCOTP CTRL OTP Controller The On-Chip OTP controller(OCOTP_ctRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCoTP CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The oCoTP_CtRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent nonvolatility 1. MX 8QuadXPlus and 8 DualXPlus automotive and Infotainment Applications Processors, Rev. 0, 11/2018 10 PRELIMINARY NXP Semiconductors

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