verilog_tutorial.pdfVerilog HDL Tutorial, 完整，英文，简单

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详细说明：Verilog HDL Tutorial, 完整，英文，简单易懂，语法等。INTRODUCTION CHAPTER 1 www.asic-world.com ● Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE(HDL). a hardware description Language is a language used to describe a digital system, for example, a network switch, a microprocessor or a memory or a simple flip-flop This just means that, by using a HDL one can describe any hardware(digital ) at any level D DEF CLK ww.asic-wond com D flip-flop Code 2module d_ff(d, clk, q, q bar input d, clk output q, a bar; swire d, clk greg a, a_bar; always(posedge clk q 11 qbar<=ld 12end 14endmodule One can describe a simple Flip flop as that in above figure as well as one can describe a complicated designs having 1 million gates. Verilog is one of the HDL languages available in the industry for designing the Hardware. Verilog allows us to design a digital design at Behavior Level Register Transfer Level(RTL), Gate level and at switch level. Verilog allows hardware designers to express their designs with behavioral constructs, deterring the details of implementation to a later stage of design in the final desig Many engineers who want to learn verilog most often ask this question, how much time it will take to learn Verilog?, Well my answer to them is"It may not take more then one week, if you happen to know at least one programming language o Design Styles Verilog like any other hardware description language, permits the designers to design a design in either Bottom-up or Top-down methodology x Bottom-Up Design The traditional method of electronic design is bottom -up. Each design is performed at the gate-level using the standard gates Refer to the Digital Section for more details)With increasing www.asic-world.com INTRODUCTION complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity Top-Down Design The desired design-style of all designers is the top-down design. a real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design due to this fact most designs are mix of both the methods, implementing some key elements of both design styles y Figure shows a Top-Down design approach. Specification High Level Design Low Level Design RTL Coding Functional verification Logic Synthesis Gate Level simulation Place And route Fabrication Post si validation w,asic-wond, com Abstraction Levels of Verilog Verilog supports a design at many different levels of abstraction. Three of them are very important Behavioral level www.asic-world.com INTRODUCTION Register-Transfer Level · Gate Leve s Behavioral level This level describes a system by concurrent algorithms(Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other Functions, Tasks and always blocks are the main elements. There is no regard to the structural realization of the design Register-Transfer Level Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RtL design contains exact timing possibility, operations are scheduled to occur at certain times. Modern definition of a RtL code is "any code that is synthesizable is called rtl code' Gate Level Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values(0,1,X Z). The usable operations are predefined logic primitives(AND, OR, Not etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend www.asic-world.com INTRODUCTION NOTES www.asic-world.com INTRODUCTION HISTORY OF VERILOG CHAPTER 2 www.asic-world.com HISTORY OF VERILOG O History Of Verilog Verilog was started initially as a proprietary hardware modeling language by gateway design Automation Inc. around 1984. It is rumored that the original language was designed by taking features from the most popular HDL language of the time, called hilo as well as from traditional computer language such as C. At that time, Verilog was not standardized and the language modified itself in almost all the revisions that came out within 198 4 to 19 90 Verilog simulator was first used beginning in 1985 and was extended substantially through 1987. The implementation was the verilog simulator sold by gateway. The first major extension was Verilog-XL, which added a few features and implemented the infamous "XL algorithm"which was a very efficient method for doing gate-level simulation The time was late 1990. Cadence Design System, whose primary product at that time included Thin film process simulator, decided to acquire gateway automation System. Along with other Gateway product, Cadence now became the owner of the Verilog language, and continued to market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the top-down design methodology, using Verilog. This was a powerful combination In 1990, Cadence recognized that if verilog remained a closed language, the pressures of standardization would eventually cause the industry to shift to VHDL. Consequently, Cadence organized Open Verilog International (ovi), and in 1991 gave it the documentation for the verilog Hardware Description Language. This was the event which"opened"the language OVi did a considerable amount of work to improve the Language Reference Manual(LRM) clarifying things and making the language specification as vendor-independent as possible Soon it was realized, that if there were too many companies in the market for Verilog, potentially everybody would like to do what gateway did so far -changing the language for their own benefit This would defeat the main purpose of releasing the language to public domain. As a result in 1994, the IEEE 1364 working group was formed to turn the ovi Lrm into an IEEE standard. This effort was concluded with a successful ballot in 1995, and Verilog became an IEEE standard in December. 1995 When Cadence gave OVi the LRM, several companies began working on Verilog simulators. In 1992, the first of these were announced, and by 1993 there were several verilog simulators available from companies other than cadence the most successful of these was vcs, the verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed to an interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but simulation execution speed was much faster In the meantime, the popularity of Verilog and PLl was rising exponentially. Verilog as a HDL found more admirers than well-formed and federally funded VHDL. It was only a matter of time before people in ovi realized the need of a more universally accepted standard accordingly the board of directors of oVi requested iEEE to form a working committee for establishing Verilog as an IEEE standard. The working committee 1 364 was formed in mid 1993 and on october 14, 1993, it had www.asic-world.com HISTORY OF VERILOG its first meeting The standard, which combined both the verilog language syntax and the Pli in a single volume, was passed in May 1995 and now known as IEEE Std 1364-1995 After many years, new features have been added to Verilog, and new version is called verilog 2001. This version seems to have fixed lot of problems that Verilog 1995 had. This version is called 1364-2000 Only waiting now is that all the tool vendors implementing it www.asic-world.com HISTORY OF VERILOG

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