MSP430F149数据手册.pdf这是MSP430F149数据手册，方便你们下载，也不要到处去找了

文件名称: MSP430F149数据手册.pdf

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详细说明：这是MSP430F149数据手册，方便你们下载，也不要到处去找了。MSP430X13XMSP430X14XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 pin designation, MSP430F147, MSP430F148, MSP430F149 PM. PAG RTD PACKAGE (TOP VIEW) A K8X阝良F平P2文p 64636261605958575655545352515049 DVcc h1 48 P5.4/MCLK P63/A3h2 47 P5.3/UCLK1 46P52/SOM|1 P65/A54 45P51/SMo1 P6.6/A6 h5 440 P5.0/STE1 P6.7A7∏6 43 P4.7/TBCLK REF 42[P46TB6 XN囗8 41P45/TB5 X○UT囗9 40P44/TB4 39P43/TB3 VREF. WeRE卩1 38P42/TB2 P1O/ TACLK凵12 37凵P41/TB1 P11/TA0口13 36P40/TB0 P12TA1口14 35 P3.7/URXD1 P1.3/TA2 340 P3.6/UTXD1 14/ SMCLK囗16 33 P3. 5/URXDO 17181920212223242526272829303132 ■■■■■■■■■■■ 0"00 M 多78 TEXAS NSTRUMENTS POST OFFICE BOX 655303 !DALLAS TEXAS 75265 MSP430X13XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 pin designation, MSP430F1471, MSP430F1481, MSP430F1491 PM. RTD PACKAGE (TOP VIEW) HUOBA75P 64636261605958575655545352515049 DVCC 480 P5.4/MCLK P63h2 47 P5.3/UCLK1 P643 46「P52OM|1 P6.5∏4 45[P5.1/Mo1 P66日5 44P50TE1 P676 43囗P47 TBCLK Reserved 7 42P46TB6 XIN 41P45TB5 XOUT [9 40P44TB4 39P43/TB3 DVss 11 38P42B2 P1O/TACLK 37P41B1 P1.1丌A013 65凵P40TB0 P12/A114 35凵P37/URXD1 P13/A215 340 P3.6/UTXD1 P1.4/SMCLK 33凵P35URXD0 17181920212223242526272829303132 ■■■■■■■■■■■■■l 60""0 分个分 M A1A42P 4 中 TEXAS INSTRUMENTS POST OFFICE BOX 655303 ?DALLAS TEXAS 75265 MSP430X13XMSP430X14XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 functional block diagrams MSP430x13x XIN XOUT DVCC DVSS A AVss RST/NMI P1 P2 P3 P4 P5 P6 8 参ACLK O Port 1/21/0 Port 3/41/0 Port 5/6 16 I/Os > SMCLK 8KB Flash 2-Bit XT2OUT Interrupt <10μ S Cony MAB 4 Bit JTAGMAB, MEABIt T6-Bi MCB cL. 16 Reg Bus MDB. 8 B Con TCK Timer b3 POR Comparator USARTO DI/TCLK 3 CC Reg 3 CC Reg UART Mode SPI Mode TDO/TDI MSP430x14x XIN XOUT DVCC DVSs AVO RST/NMI ⊥L二⊥L 主主主主主 Oscillator H ACLK 60KB Flash 2KB RAM ADC12 o Port 1/21/0 Port 3/41/0 Port 5/6 System H SMCLK 48KB Flash 16 OS 16|Os 2KB RAM 12-Bt XT2QUT Interrupt 2KB Flash 1KB RAM <10 us Conv Capability MCLK Test MAB, M& Bit16-Bit JTAG cL. 16 Reg MDME部B16-Bit Bus Hardware Watchdog Timer_B7∏Ti POR marat USARTO USART TDI/TCLK eg 3 CC Reg UART Mode UART Mode 15/16-Bit Shadow SPI Mode SPl Mad TDO/TDI TEXAS NSTRUMENTS POST OFFICE BOX 655303 !DALLAS TEXAS 75265 MSP430X13XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 functional block diagrams(continued) MSP430×14×1 XIN XOUT DVCC DVSs AVCC AVss RST/NMI P1 P2 P3 P4 P5 P6 ⊥_L二⊥二二L二二二二主主主 Oscillator H ACLK 60KB Flash 2KB RAM /O Port 3/4 1/0 Port 5/6 16/Os 16O Clock SMCLK 48KB Flash 2KB RAM XT2OU Interrupt 32KB Flash 1KB RAM MCL AB,下BBt16-Bt JTAG cL. 16 Reg. BUs MDB. 8 Bit Hardware Watchdog H Timer_ B Timer A POR Comparator USART1 TDITCLK 7 CC Reg 3 CC Reg UART Mode UART Mode MAC, MACS Shadow SPI Mode SPI Mode 中 TEXAS INSTRUMENTS POST OFFICE BOX 655303 ?DALLAS TEXAS 75265 MSP430X13XMSP430X14XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 Terminal Functions MSP430X13x, MsP430X14x ERMINAL DESCRIPTION NAME A CC 4 Analog supply voltage, positive terminal Supplies the analog portion of the analog-to-digital converter. Analog supply voltage, negative terminal Supplies the analog portion of the analog-to-digital converter DVCC Digital supply voltage, positive terminal. Supplies all digital parts 63 Digital supply voltage, negative terminal. Supplies all digital parts P1.0/TACLK 12 General-purpose digital l/ O pin/Timer A, clock signal TACLK input P1.1/A0 General-purpose digital lo pin/Timer A, capture: CCIOA input, compare: Outo output/BSL transmit P1.2/TA1 14 o General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/A2 15 l0 General-purpose digital l/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 1o General-purpose digital I/O pin/SMCLK signal output 5/TA0 17 l0 General-purpose digital I/O pin/Timer_A, compare: Outo output P1.6/TA1 18 l0 General-purpose digital I/O pin/Timer_A, compare: Out1 output P1.77A2 19 lo General-purpose digital I/0 pin/Timer_A, compare: Out2 output/ P2.0/ACLK 20 l0 General-purpose digital I/O pin/ACLK output P2.1/TAINCLK vo General-purpose digital l/O pin/Timer_A, clock signal at INCLK 2 /CAOUT/TA0 22 vO General-purpose digital I/O pin/ Timer_A, capture: CCIOB input/Comparator_A output /BSL receive P2.3/CAO/TA1 23 1 0 General-purpose digital 1/0 pin/Timer_A, compare: Out1 output/Comparator_ A input P2.4/CA1/TA2 24 I0 General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_ A input P2.5/RoSC 25 vo General-purpose digital l /O pin/input for external resistor defining the DCO nominal frequency 2. 6/ADC12CLK 1o General-purpose digital I/O pin/conversion clock 12-bit ADC P2.7/TA0 7 lo General-purpose digital I/O pin/Timer_A, compare: Outo output P3.0/STEO 28 10 General-purpose digital I/O pin/slave transmit enable USARTO/SPImode P3.1/S|Mo0 29 l0 General-purpose digital l/O pin/slave in/master out of USARTO/SPI mod P3.2/sOM|0 30 10 General-purpose digital l/O pin/slave out/master in of USARTO/SPI mode P3.3/UCLKO 10 General-purpose digital I/O/USARTO clock: external input-UART or SPI mode SPI mode P3.4/UTXDO 32 10 General-purpose digital I/O pin/transmit data out USARTO/UART P3.5/URXDO 33 l0 General-purpose digital l/ O pin/receive data in USARTOUART mode P3.6/UTXD1 1o General-purpose digital l/O pin/transmit data out USART1UART mode P3.7/URXD1? 35 10 General-purpose digital I/O pin/receive data in USART1/UART mode P4, 0/TBO 1o General-purpose digital I/O pin/Timer_B, capture: CCIOA or CCIOB input, compare: Outo output P4.1/B1 37 vo General-purpose digital I/O pin/Timer_B, capture CCllA or CCl1B input, compare: Out1 output P4.2/B2 1o General-purpose digital I/O pin/Timer_B, capture: CC12A or CC12B input, compare: Out2 output P43/B3? General-purpose digital lO pin/Timer B, capture: CCI3A or CCI3B input, compare: Out3 output P44/TB4? 0 l0 General-purpose digital l/O pin/Timer_B, capture: CCl4A or CCI4B input, compare: Out4 output P45/TB5? 41 1o General-purpose digital I/O pin/Timer_B, capture CCI5A or CCI5B input, compare: Out5 output P46/B6? 42 l0 General-purpose digital l/O pin/ Timer B, capture: CCIGA or CCI6B input, compare: Out6 output P4.7/TBCLK 3 lo General-purpose digital I/O pin/Timer_B, clock signal TBCLK input P5.0/STE1? General-purpose digital 1o pin/slave transmit enable USART1/SPI mode P5.1/SIM01 45 l0 General-purpose digital I/O pin/slave in/master out of USART 1/SPI mode P5.2/SOM1? 6 0 General-purpose digital I/O pin/slave out/master in of USART1/SPI mode P5.3/UCLK1? 47l0 General-purpose digital I/O pin/USART1 clock: external input-UART or SPI mode, output SRI mode P5.4/MCLK lo General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 vo General-purpose digital I/O pin/submain s K output 14x devices only 中 TEXAs NSTRUMENTS POST OFFICE BOX 655303 !DALLAS TEXAS 75265 MSP430X13XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 Terminal Functions(Continued) MSP430×13×,MSP430X14X( continued) O DESCRIPTION 正E JAM NO P5. 6/ACLK 1OGeneral-purpose digital o pin/auxiliary clock ACLK output P5. 7/TBOUTH 10 General-purpose digital 1/0 pin/switch all PWM digital output ports to high impedance- Timer_B7: TB0 to P6.0/A0 59 l0 General-purpose digital 1/0 pin/analog input a0 12-bit ADC P6.1/A General-purpose digital 1O pin/analog input a1 P6.2/A2 61v0 General-purpose digital I/O pin/analog input a2 12-bit ADC P6.3/A3 2 l0 General-purpose digital l/O pin/analog input a3 12-bit ADC P64/A4 1o General-purpose digital I/O pin/analog input a4 12-bit ADC P65/A5 4 l0 General-purpose digital O pin/analog input a5 12-bit ADC P66/A6 General-purpose digital l/ 0 pin/analog input a6 12-bit ADC P6.7/A7 10 General-purpose digital V/O pin/analog input a7 12-bit ADC RSTZNMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start(in Flash devices TCK 57 Test clock. tCK is the clock input port for device programming test and bootstrap loader start(in Flash devices TDI/TCLK 55 Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. DO/TDI 1o Test data output port. TDO/TDI data output or programming data input terminal I Test mode select. TMS is used as an input port for device programming and test eREF+ I Input for an external reference voltage to the ADC 7 o Output of positive terminal of the reference voltage in the ADC Ne REF Negative terminal for the AdC s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN Input port for crystal oscillator XT1 Standard or watch crystals can be connected XOUT 9 o Output terminal of crystal oscillator XT1 XT2IN 53 Input port for crystal oscillator XT2. Only standard crystals can be connected. XT2OUT o Output terminal of crystal oscillator XT2 QFN Pad naNA QFN package pad connection to DV ss recommended 中 TEXAS INSTRUMENTS POST OFFICE BOX 655303 ?DALLAS TEXAS 75265 MSP430X13XMSP430X14XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 Terminal Functions MSP430x14x1 ERMINAL DESCRIPTION NAME A CC 4 analog supply voltage, positive terminal Analog supply voltage, negative terminal DVCC Digital supply voltage, positive terminal. Supplies all digital parts 63 Digital supply voltage, negative terminal. Supplies all digital parts P1.0/TACLK 12 General-purpose digital l/0 pin/Timer A, clock signal TACLK input P1.1/A0 General-purpose digital lo pin/Timer A, capture: CCIOA input, compare: Outo output/BSL transmit P1.2/TA1 14 o General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/A2 15 l0 General-purpose digital l/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 1o General-purpose digital I/O pin/SMCLK signal output 5/TA0 17 l0 General-purpose digital I/O pin/Timer_A, compare: Outo output P1.6/TA1 18 l0 General-purpose digital I/O pin/Timer_A, compare: Out1 output P1.77A2 19 lo General-purpose digital l/O pin/Timer_A, compare: Out2 output P2.0/ACLK 20 l0 General-purpose digital I/O pin/ACLK output P2.1/TAINCLK vo General-purpose digital l/O pin/Timer_A, clock signal at INCLK 2 /CAOUT/TA0 22 vO General-purpose digital I/O pin/ Timer_A, capture: CCIOB input/Comparator_A output /BSL receive P2.3/CAO/TA1 23 1 0 General-purpose digital 1/0 pin/Timer_A, compare: Out1 output/Comparator_ A input P2.4/CA1/TA2 24 I0 General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_ A input P2.5/RoSC 25 vo General-purpose digital l /O pin/input for external resistor defining the DCO nominal frequency 1o General-purpose digital I/O pin P2.7/TA0 7 lo General-purpose digital I/O pin/Timer_A, compare: Outo output P3.0/STEO 28 10 General-purpose digital I/O pin/slave transmit enable USARTO/SPImode P3.1/S|Mo0 29 l0 General-purpose digital l/O pin/slave in/master out of USARTO/SPI mod P3.2/sOM|0 01/0 General-purpose digital l/O pin/slave out/master in of USARTO/SPI mode P3.3/UCLKO 10 General-purpose digital I/O/USARTO clock: external input-UART or SPI mode SPI mode P3.4/UTXDO 32 10 General-purpose digital I/O pin/transmit data out USARTO/UART P3.5/URXDO 33 l0 General-purpose digital l/ O pin/receive data in USARTOUART mode P3. 6/UTXD1 1o General-purpose digital l/O pin/transmit data out USART1UART mode P3.7/URXD1 35 10 General-purpose digital I/O pin/receive data in USART1/UART mode P4, 0/TBO 1o General-purpose digital I/O pin/Timer_B, capture: CCIOA or CCIOB input, compare: Outo output P4.1/B1 37 vo General-purpose digital I/O pin/Timer_B, capture CCllA or CCl1B input, compare: Out1 output P4.2/B2 1o General-purpose digital I/O pin/Timer_B, capture: CC12A or CC12B input, compare: Out2 output P4.3/TB3 General-purpose digital lO pin/Timer B, capture: CCI3A or CCI3B input, compare: Out3 output P4.4/TB4 0 l0 General-purpose digital l/O pin/Timer_B, capture: CCl4A or CCI4B input, compare: Out4 output P4.5/TB5 41 1o General-purpose digital I/O pin/Timer_B, capture CCI5A or CCI5B input, compare: Out5 output P4.6/TB6 42 l0 General-purpose digital l/O pin/ Timer B, capture: CCIGA or CCI6B input, compare: Out6 output P4.7/TBCLK 3 lo General-purpose digital I/O pin/Timer_B, clock signal TBCLK input P5.0/STE1 General-purpose digital 1o pin/slave transmit enable USART1/SPI mode P5.1/S|Mo1 45 l0 General-purpose digital I/O pin/slave in/master out of USART 1/SPI mode P5.2/SOMI1 6 0 General-purpose digital I/O pin/slave out/master in of USART1/SPI mode P5.3/UCLK1 47l0 General-purpose digital I/O pin/USART1 clock: external input-UART or SPI mode, output SRI mode P5.4/MCLK lo General-purpose digital I/O pin/main system clock MCLK output 5/SMCLK 49 vo General-purpose digital I/O pin/submain s K output 中 TEXAs NSTRUMENTS POST OFFICE BOX 655303 !DALLAS TEXAS 75265 MSP430X13XMSP430X 14x1 MIXEDSIGNALMICROCONTROLLER SLAS272F-JULY 2000-REVISED JUNE 2004 Terminal Functions(Continued) MSP430X14x1(continued) TERMINAL O DESCRIPTION 正E JAM NO P5. 6/ACLK 1OGeneral-purpose digital o pin/auxiliary clock ACLK output P5. 7/TBOUTH 10 General-purpose digital 1/0 pin/switch all PWM digital output ports to high impedance- Timer_B7: TB0 to P6.0 59 V0 General-purpose digital l/O pin General-purpose digital lO pin P6.2 61 1o General-purpose digital l/O pin P6.3 2 l0 General-purpose digital W/O pin P64 1o General-purpose digital l/O pin P65 4 l0 General-purpose digital l/O pin P6.6 General-purpose digital O pin P6.7 1o General-purpose digital V/O pin RSTZNMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start(in Flash devices TCK 57 Test clock. tCK is the clock input port for device programming test and bootstrap loader start(in Flash devices TDI/TCLK 55 Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. DO/TDI 1/o Test data output port. TDO/TDI data output or programming data input terminal I Test mode select. TMS is used as an input port for device programming and test DVss I Connect to DV ss Reserved 7 Reserved, do not connect externally DVSS Connect to DV ss XIN 81mputportforcrytalsclaor0xT1standardorwachcrstalseanbeconecded XOUT o Output terminal of crystal oscillator XT1 XT2IN I Input port for crystal oscillator XT2. Only standard crystals can be connected XT2OUT 52 o Output terminal of crystal oscillator XT2 QFN Pad nANA QFN package pad connection to DV ss recommended 中 TEXAS INSTRUMENTS POST OFFICE BOX 655303 ?DALLAS TEXAS 75265

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