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详细说明：arm手册 pdfDate Versio Changes 29/0312016A.a Confidential Beta release. limited circulation Beta DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved 0-ii1 1D29o32019 Non-confidential Armv8-M Architecture Reference Manual Copyright o 2015-2019 Arm Limited or its affiliates. All rights reserved. The copyright statement reflects the fact that some draft issues of this document have been released. to a limited circulation Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. 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Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arms trademark usage guidelines at http://www.arm.com/company/policies/trademarks Copyright o 2015-2019 Arm Limited (or its affiliates). All rights reserved Arm Limited. Company 02557590 registered in England 110 Fulbourn Road, Cambridge, England cbl 9NJ LES-PRE-20349 Confidentiality Status This document is Non-confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that arm delivered this document to DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved D29o32019 Non-confidential Product status The information in this document is final, that is for a developed product Web address http://www.arm DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved 1D29o32019 Non-confidential Contents Armv8-M Architecture Reference Manual Release informatic ArmV8-M Architecture Reference Manual Proprietary Notice Confidentiality s Product status Web Address Preface About this book Using this book XXXVIIl Conventions Typographical conventions Signals Numbers Pseudocode descripti Assembler syntax descriptions Additional reading Arm publications X Other publications Feed back xlii Feedback on this book xIL Part A Armv8-M Architecture Introduction and overview Chapter A Introduction A1.1 Document layout and terminology 46 A1.1. 1 Structure of the document 46 A1.1.2 Scope of the document 47 A1.1.3 Intended audience 47 A1. 1.4 Terminology, phrases 47 A1. 1.5 Terminology, Armv8-M specific terms A1.2 About the Armv8 architecture, and architecture profiles 49 A1. 3 The Armv8-M architecture profile 50 A1.3. 1 Security Extension 50 A1.3.2 MPU model 50 A1.3.3 Nested Vector Interrupt controller A1.3. 4 Stack pointers 50 A1.3.5 The Armv8-M instruction set 51 A1.3.6 Debug .51 A1.3.7 Reliability, Availability, and Serviceability 51 A1.4 ArmV8-M variants 52 A1.4.1 Features of Armv8 1-M A1. 4.2 Interaction between MVE and the Floating-point Extension in Armv8 1-M 58 Part B ArmV8-M Architecture rules Chapter B1 Resets DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved D29o32019 Non-confidential Contents B1.1 Resets Cold reset, and Warm reset 62 Chapter b2 Power Management B2.1 Power management 64 B2.1. 1 The Wait for Event(WFE)instruction 64 B2. 1.2 The Event registe 64 B2. 1.3 The Wait for Interrupt(WFI) instruction 65 B2.2 Sleep on exit Chapter B3 Programmers Model B3. PE modes, Thread mode and Handler mode B3. 2 Privileged and unprivileged execution B3.3 Registers B3. 4 Special-purpose CONT ROL register 73 B35 XPSR. APSR. IPSR and EPSR 74 B3.5.1 Interrupt Program Status Register(IPSR 75 B3.5.2 Execution Program Status Register(EPSR B3.6 Security states: Secure state, and Non-secure state B3.7 Security states and register banking between Security states 78 B3.8 Stack pointer B3. 9 EXception numbers and exception priority numbers 81 B3. 10 EXception enable, pending, and active bits 84 B3. 1 1 Security states, exception banking 86 B3.12 Faults 88 B3.13 Priority model 92 B3. 14 Secure address protection B3. 15 Security state transitions 97 B3.16 Function calls from Secure state to Non-secure state 99 B3.17 Function returns from Non -secure state 100 B3. 18 EXception handling 102 B3.19 EXception entry, context stacking 104 B3. 20 Exception entry, register clearing after context stacking 112 B3.21 Stack limit checks 113 B3.22 Exception return B3.23 Integrity signature 120 B3.24 Exceptions during exception entry 121 B3.25 Exceptions during exception return 123 B3.26 Tail-chai 124 B3.27 Exceptions, instruction resume, or instruction restart ,,127 B3.28 Low overhead lo 130 B3.29 Branch future 133 B3.30 Vector tables 135 B3. 31 Hardware-controlled priority escalation to HardFault 137 B3.32 Special-purpose mask registers, PRIMASK, BASEPRI, FAULTMASK, for con figurable priority boosting 138 B3.33 Lockup B3 33.1 Instruction-related lockup behavior 140 B3.33.2 Exception- related lockup behavior 142 Errors when unstacking state on exception return 144 B3. 34 Data independent timing B3.35 Context Synchronization event 149 B3.36 Coprocessor suppe 150 Chapter B4 Floating-point Support B4.1 The optional Floating-point Extension, FPV5 152 DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved D29o32019 Non-confidential Contents B4.2 About the Floating-point Status and Control Registers 154 B4.3 Registers for Floating-point data processing, So-S31, or DO-D15 155 B4.4 Floating-point standards and terminology 156 B4.5 Floating-point data representable 157 B4.6 Floating-point encoding formats, half-precision, single-precision, and double precision 158 B4.7 The IEEE 754 Floating-point exceptions 160 B4.8 The flush-to-zero mode 161 B4.8. 1 The Flush to zero mode half-precision calculations 162 B4.9 The Default Nan mode, and Nan handling 163 B4.10 he Default naN 164 B4.11 Combinations of Floating-point exceptions 165 B4.12 Priority of Floating-point exceptions relative to other Floating-point exceptions 166 Chapter B5 Vector Extension B5.1 Vector Extension operation 168 B52 Vector register file 169 B53 anes B54 Beats 171 B55 Exception state B56 Predication/conditional execution 177 B5.6. 1 Loop tail predication 177 B5.6.2 VPT predication 178 B5.6.3 Eftects of predication ....181 B5.6. 4 T block 183 B5.7 MVE interleaving/de- interleaving loads and stores 184 Chapter B6 Memory Model B6. 1 Memory accesses ........187 B6.2 Address space 188 B63 Endianness 189 B6. 4 Alignment behavior 191 B65 Atomicit' 192 B6.5. 1 Single-copy atomicity 192 B6.5.2 Multi-copy atomicity 192 B6.6 Concurrent modification and execution of instructions 194 Access rights 196 B6.8 Observability of memory accesses 198 B6.9 Completion of memory accesses ,,,,,200 B6. 10 Ordering requirements for memory accesses ....201 B6. 11 Ordering of implicit memory accesses .202 B6. 12 Ordering of explicit memory accesses 203 B6. 13 Memory barriers B6.13.1 Instruction Synchronization barrier 204 36. 13.2 Data Memory barrier 204 B6 13.3 Data Synchronization Barrier 05 B6 13.4 Consumption of Speculative Data Barrier 206 B6. 13.5 Physical Speculative Store Bypass Barrier 207 B6. 13.6 Speculative Store Bypass Barrier 207 B6.13.7 Synchronization requirements for System Control Space 208 B614 Normal meme 209 B6.15 Cacheability attributes B6.16 Device mer 212 B6.17 Device memory attributes 214 B6 17.1 Gathering and non-Gathering Device memory attributes .215 DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved D29o32019 Non-confidential Contents B6 17.2 Reordering and non -Reordering Device memory attributes 215 B6. 17.3 Early Write Acknowledgement and no Early Write Acknowledgement Device memory attributes 216 B6. 18 Shareability domains 217 B6.19 Shareability attributes 219 B6.20 Memory access restrictions B6.21 Mismatched memory attribute 21 B6.22 Load-EXclusive and Store- Exclusive accesses to Normal memory 223 B6.23 Load-Acquire and Store-Release accesses to memory B6.24 Caches B6.25 Cache identification 228 B6.26 Cache visibilit 229 B6.27 Cache coherency 230 B6.28 Cache enabling and disabling B6.29 Cache behavior at reset 232 B6.30 Behavior of Preload Data(PLD) and Preload Instruction( PLl)instructions with caches 233 B6.31 Branch predictors 234 B6.32 Cache maintenance operations 235 B6.33 Ordering of cache maintenance operations 239 B6. 34 Branch predictor maintenance operations 240 Chapter B7 The System Address Map B71 System address map 242 B7.2 The System region of the system address map .243 B7.3 The System Control Space(SCS 246 Chapter B8 Synchronization and Semaphores B8.1 Exclusive access instructions 248 B8.2 The local monitors 249 B8.3 The global monitor .251 B8.3.1 Load-Exclusive and Store-Exclusive 252 B8.3.2 Load-Exclusive and Store-Exclusive in Shareable memory 253 B8. 4 Exclusive access instructions and the monitors 255 B8.5 Load-Exclusiye and store-Exclusive instruction constraints Chapter B9 The Armv8-M Protected Memory System Architecture B9.1 Memory Protection Unit 259 B9.2 262 B9. 3 Security attribution unit (SAU) .266 B9.4 IMPLEMENTATION DEFINED Attribution Unit (IDAU 267 Chapter B10 The System Timer, Sys Tick B10.1 The system timer, SysTick 269 Chapter B11 Nested Vectored Interrupt Controller B11.1 Nvic definition ....272 B11.2 NVIC operation 273 Chapter B12 Debug B12.1 Debug feature overview 276 B12.1.1 Debug mechanisms B12.1.2 Debug resources ..,.280 B12.1.3 Trace 281 B12.2 Accessing debug features ,..,,283 B12.2.1 ROM table 283 DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved D29o32019 Non-confidential B12. 2.2 Debug System registers 285 B12. 2.3 Core Sight and identification registers 286 B12.3 Debug authentication inter 288 B12.3.1 Halting debug authentication 289 B12.3.2 Non-invasive debug authentication 292 B12.3.3 DebugMonitor exception authentication 294 B12.3.4 Unprivileged DebugMonitor Authentication 295 B12.3.5 DAP access permissions B12.4 Debug event behavior 301 B12.4.1 About debug events B12.4.2 Debug stepping 307 B12.4.3 Vector catch 311 B12. 4. 4 Breakpoint instructi 314 B12.4.5 External debug request .315 B12.5 Debug state 317 B12.6 Exiting Debug state 321 B12.7 Multiprocessor support B12.7.1 Cross-halt event 322 B12.7.2 External restart request Chapter B13 Debug and Trace Components B13.1 Instrumentation trace macrocell .324 B13.1.1 About the ITm 324 B13.1.2 M operation 325 B13.1.3 T imestamp support 327 B13.1.4 Synchronization support 331 B13.1.5 Continuation bits 331 B13.2 Data Watchpoint and Trace unit 333 B13.2. 1 About the dWt B13.2.2 DWT unit operation ..334 B13.2.3 Constraints on programming dwt comparators B13.2.4 CMPMATCH trigger events 342 B13.2.5 Matching in detail 342 B13.2.6 DWT match restrictions and relaxations 346 B13.2.7 DWT trace restrictions and relaxations 348 B13.2.8 CYcCNT cycle counter and related timers 349 B13.2. 9 Profiling counter support 35 B13.2.10 Program Counter sampling support 352 B13.3 Embedded Trace Macrocell B13.4 Trace Port Interface Unit 356 B13.5 Flash Patch and breakpoint unit ..358 B13.5.1 About the FPb unit B13.5.2 FPB unit operation 358 B13.5.3 Cache maintenance 361 Chapter B14 The Performance Monitoring Unit Extension B14.1 Counters 363 B14.2 Accuracy of the performance counters 364 B14.3 Security, access, and modes 365 B14. Attributability 366 B145 Coexistence with the dwt performance monitors 367 B14.6 Interrupts and Debug events B14.7 List of supported architectural and microarchitectural events .369 B14.8 Generic architectural and microarchitectural events 375 B14.8.1 Ll CACHE REFILL (Levek instruction cache refi .375 DDI0553B g Copyright C 2015-2019 Arm Limited or its affiliates. All rights reserved 1D29o32019 Non-confidential

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