TDA7708_Rev7_15Dec2017.pdfFeatures  AEC-Q100 qual

文件名称: TDA7708_Rev7_15Dec2017.pdf

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详细说明：Features  AEC-Q100 qualified  AM/FM reception with digital IF processing  Fully automotive grade CMOS design  AM/FM Band  Low-IF, DSP-based architecture  Very high dynamic range built-in IF-ADC  Minimum external component count  Very small footprint package  Multipath noise mitigation processing  RDS demodulation with group and block synchronization  Compatible with HD-Radio™ and DRM  Digital Audio Output  Fully RoHS-compliantTDA7708 Contents 3.1 Absolute maximum ratings……,…,………36 3.2 Thermal data 36 3.3 General key parameters 36 3.4 Electrical characteristics 37 3. 4.1 FM-section 34.2 AM-section 38 3.4.3 VcO 3.4.4 Phase locked loop 39 3.4.5 F ADC 39 3. 4. 6 Audio dac 3.4.7 Digital l/O interface pins 39 3.4.82C interface 43 3.4.9 SPI interface 3.5 Overall system performance 44 3.5.1 FM system performance 44 3.5.2 AM MW system performance 46 3.5.3 AM LW system performance .48 3.5.4 AM SW overall system performance 48 3.5.5 WX system performance Q 4 AI Application schematic …50 5 Package information . 5.1 VFQFPN-64(9x9x1.0mm) package information 6 Revision history ■■■■■■■■口■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■ 53 DocID029616 Rev 7 3/54 List of tables TDA7708 List of tables Table 1: Device summary.............. Table 2 Pins description .⊥: Table 3: Status information for In-phase data(si)..... 16 Table 5: SAl BB timing values((16 bit)+Q(16 bit)and Si(16 bit)+ Sq(16 bit))for SoC-based...16 Table 4: Status information for Quadrature-phase data(Qi) AM/FM/DRM/HD-Radio M, I/Q and status information are multiplexed on a single data line . ...17 Table 6: SAl BB timing values(normal mode: I(16 bit)+ si(16 bit)+Q(16 bit)+sQ(16 bit)on a single data line) for hd- Radio....,…,,…, 17 Table 7: SAl BB timing values(normal mode: I(16 bit+ Q(16 bit on a single data line )for DCOP-based HD-Radio M 18 Table 8: JESD204B transmitter main clocks 19 Table 9: Status information for JESD204b interface Status High ( sh)in 32-bit mode 19 Table 10: Status information for JESD204b interface Status Low(SL)in 32-bit mode 9 Table 11: Status information for JESD204b interface for l&Q data in 16-bit mode 19 Table 12: Audio 12S configuration overview Table 13: Audio 12S interface timing in reception mode 23 Table 14: Audio 12S interface timing in transmission mode Table 15: Control interface configuration pins Table 16: Mapping of sPl pins to l2C pi 9 Table 17: Power-supply pin description 33 Table 18: Start-up sequence timing Table 19: Reset timing 35 Table 20: Absolute maximum ratings 6 Table 21: thermal data 36 Table 22: General key parameters 6 Table 2 3 FM- section 37 Table 24: AM-section 8 Table 25 vco 38 Table 26: Phase locked loop Table 27: F adc 39 Table 28: Audio dac 39 Table 29: Digital l/o interface pins 39 Table 30 LVDS-12S base-band transmitter characteristics 40 Table 31 LVDS-2S base-band receiver characteristics 42 Table 32. JesD204b base-band transmitter characteristics Table 33 2C interface ,43 Table 34: SPI interface timing 44 Table 35: FM system performance 45 Table 36: AM MW system performance 46 Table 37: AM-LW system performance 48 Table 38: AM-SW system performance 48 Table 39: WX system performance 49 Table 40: VFQFPN-64(9x9x10 mm)package mechanical data Table 41: Document revision history 4/54 DocDo29616 ReV 7 TDA7708 List of fiqures List of figures Figure 1: Functional block diagram Figure 2: Pin out diagram(top view) Figure 3: Crystal oscillator block diagram 13 Figure 4: Architecture example for a HD-Radio m standard receiver based on dCOP with 12S base-band data input 14 Figure 5: 12S standard configuration with single-ended signals Figure 6: 12S standard configuration with LVDS signals 15 igure 7: 12S single-port configuration 16 Figure 8: SAl BB waveforms for SoC-based a M/FM/DRM/HD-Radio M the data are the complex phase/quadrature signals l(16 bit Q(16 bit)and their corresponding status information Si(16 bit)+ Sq(16 bit 17 Figure 9: SAl BB waveforms for data i(16 bit) +sI(16 bit)+Q(16 bit)+sQ(16 bit)transmitted on a single data line; this configuration is used for implementing HDRadio M 17 Figure 10: SAl BB waveform for data: I(16 bit)+ Q(16 bit) transmitted on a single data line, in DCOP STA680D)-based HD-Radio N 17 Figure 11: Example Soc processor receiving the base-band signals from five RF channels based on JEsT204 B connectivity…… 18 Figure 12: JESD204b interface in analog mode(16-bit) Figure 13: JESD204B interface data padding for FM/AM/DRM 1024 kHz in analog mode 20 Figure 14: JESD204B interface data padding for FM/AM/DRM 512 kHz in Analog mode Figure 15: JESD204B interface low-rate configuration for FM/AM/DRM 20 Figure 17: Architecture example for a DRM system based on DCOP(STA660DRM)processor,s..2 Figure 16: JESD204b interface for HD-Radio M mode(16-bit) Figure 18: Coded LVDs base-band interface waveforms when TDA7708 is paired to DCOP STA66ODRM 22 igure 19: Audio 2S interface waveform and timing in reception mode 23 Figure 20: Audio 1 S interface waveform and timing in transmission mode 23 Figure 21: Audio 12S interface 16-bit data 24 Figure 22: Audio |2S interface 32/24/20/16-bit data 24 Figure 23: Signal connectivity to DCOP HD-Radio M digital CO-processor 25 Figure 25: Cumulative CIC+CFIR Frequency response for AM/FM/HD-Radio TM(top: full bag. Figure 24: Digital-Down-Converter block diagram 26 bottom: close-up in-band view 27 Figure 26: FIR1 frequency response for AM/FM/HD-Radio M 28 Figure 27: System architecture for VICS reception 28 Figure 28: SPI interface write cycle 30 Figure 29: SPI interface read cycle 国国面国量面 30 Figure 30: SPI interface burst-read cycle 30 Figure 31: Example of data transfer on the 12C bus Figure32: Example|2 C write operation…… 32 Figure 33: Example of IC read operation ............. 32 Figure 34: Start-up sequence 34 Figure 35: Reset timing Figure 36: AM capacitive antenna dummy 38 Figure37: CMoS base- band timing diagram in half- cycle mode.……… 40 Figure 38: LVDS-transmitter pin characteristics Figure 39: LVDS-l2S base-band pin timing diagram for half-cycle mode Figure 40: LVDS-l2S base-band pin timing diagram for full- cycle mode 42 Figure 41: 12C bus timing diagram 43 Figure42: SPI interface timing..……. 44 Figure 43: FM input setup...... 44 Figure 44: AM MW input setup........ :.:.::: 46 Figure 45: AM LW input setup.............. 48 DocID029616 Rev 7 5/54 List of figures TDA7708 Figure 46: AM SW input setup 48 Figure47: Weather-band input setup…… .49 Figure 48: AM/FM application example Figure49: VFQFPN64(9X9×1.0mm) package outline…… 6/54 DocDo29616 ReV 7 TDA7708 Block diagram and pins description Block diagram and pins description Block diagram Figure 1: Functional block diagram ADC C H DRM PLL CRYSTA. HD-Radio 36.864Mz DocID029616 Rev 7 7/54 Block diagram and pins description TDAZ708 12 Pin description Figure 2: Pin out diagram(top view) gay g9巴日房5防历显日EEEE GND DIG WX VDD R REF1 FM VDD R NC匚6 GND DIG FQFPN AF1 CLK FM IN 9x9x10mm L AF1 WS SIG GND F SIG GND FM AF1 DOC VCFM□12 GP013 FAl PI012 GND RF VCC RF 33 GND DIG c.口 d GADG0507160730PS Table 2: Pins description Pin Pin name l/0Function Description Main alternate Equivalent circuit function 1 NC Not connected 2 SIG GND WX Ground Always connected to ground 3 WX N WⅩ Weather band Lna input. 8/54 DocID029616 Rev 7 TDA7708 Block diagram and pins description Main alternate Pin Pin name 10 Function Description function Equivalent circuit 4 REF1 FM FM 2.5V regulator output 5 NC 6 NC 7 NC 8 NC 9 FM IN FM FM LNA input (1) 10 SIG GND FM Ground FM signal ground.(2) 11 SIG GND FM Ground FM signal ground.(2) 12 VCC FM Supply FM power supply. 2) AM reference decoupling In 13 REF AM O AM case aM is not used it can be left unconnected 14 AM IN AM AM LNA input (1 15 GND RF Ground RF ground 16 VCC RF Supply RF 3.3V power suppl 17 REF2 Reference decoupling 2.5V 18 NC Not connected 19 GND PLL PLL ground /CC PLL PLL supply 3.3V DocID029616 Rev 7 9/54 Block diagram and pins description TDA7708 Main alternate Pin Pin name 10 Function Description function Equivalent circuit 21 XTO O Oscillator Crystal output 22 XTI Oscillator Crystal input 23 GND GLOBAL Global ground 24 VCC GLOBAl Global 3.3V power supply 25 DAC L DAC DAC output left TEST FI 26 GND DAC Ground DAc ground DAC DAC output right TEST IF Q 28 BLEND Hd blend input GPIO5 29 GPO1 vO General purpose I/o 1 CHO Q 30 BB DO VO BB l2S data0 CHO I 31 BB WS v0 BB 2S word select 32 BB CLK 10 BB 2S clock 33 GND DIG Digital I/o ground 34 NC Not connected 35 VDD IO Digital 10 3. 3V power supply 36GP|O12 10 General purpose 1 /0 12 37GP|O13 vO General purpose I/o 13 38 AlF1 DO0 audio sal data o General purpose /00 39 AlF1 DIN General Audio sal data input purpose 1/06 40 AlF1 WS General 10 Audio sal word strobe purpose 1/07 Genera 41 AlF1 CLK O Audio sal bit clock purpose 1/0 8 42 NC Not connected 43 GND DIG Digital core Ground 44 VREG 1V2 1.2V Regulator output 45 VDD R Digital power supply 46 VDD R Digital power supply 10/54 DocID029616 Rev 7

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