MT6735_PCB_Design_Guidelines-Simplified_Chinese--V

文件名称: MT6735_PCB_Design_Guidelines-Simplified_Chinese--V0_2.pdf

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上传时间: 2019-07-04

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详细说明：概述 ▪ 封装 • MT6735芯片外形尺寸 • MT6735 Footprint设计 • MT6735重要信号分布图 ▪ 一般设计建议 • 叠构(PCB stack‐up)建议 • Common Rules and Via Type • Placement Notes • MT6735 fan out ▪ High‐Speed Digital设计建议 • LPDDR3 • LPDDR2 • PDN design ▪ 其它设计建议 • MT6735 RF interface ‐ MT6169 ‐ MT6158 • MT6328(PMU) • MT6625 (BT/FM/WiFi/GPS) • USB/ MIPI/ SIM Card / T‐Card/ eMMC/Differential Pair Layout Suggestion纲目概述封装 MT6735芯片外形尺寸 MT6735 Footprint设计 MT6735重要信号分布图般设计建议叠构( PCB stack-up)建议 Common Rules and via Type Placement notes MT6735 fan out High- Speed Digital设计建议 ● LPDDR3 LPDDR2 PDN design 其它设计建议 ●MT6735 RF interface -MT6169-MT6158 MT6328(PMU) MT6625(BT/FM/WiFi/GPS USB/MIPI/SIM Card/T-Card/ eMMC/Differential Pair Layout Suggestion MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 2015/2/9 纲目概述封装 ·MT6735芯片外形尺寸 MT6735 Footprint设计 MT6735重要信号分布图般设计建议叠构( PCB stack-up)建议 Common Rules and Via Type Placement notes MT6735 fan out High- Speed Digital设计建议 ● LPDDE3 LPDDR2 PDN design 其它设计建议 ●MT6735 RE interface T6169MT6158 MT6328(PMU) MT6625(BT/FM/WiFi/GPS USB/MIPI/ SIM Card/T-Card/ eMMC/Differential Pair Layout Suggestion MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 概述 MT6735是新一代LTE智慧手机芯片,中央处理器采用安谋四杉心 Cortex53、28奈米制程,频率最高可达15GHz Dual siM Video Telephony BT/FM/i-Fi/GPS 1080p Video Playback Integrated Video Streaming 八《U优酷 com You Tube Hot Knot MT6735 13M Camera 1080p Video Record Cortex A53 1.3-1.5GHz Face Detection Smile Shot QUAD Core AP LTE Cat 4 HOT KNOT W-HSPA+ Rel 8 TD-HSPA Rel.7 4G LTE Support Tier 1 Performance CDMA/EVDO Audio/Speech/Modem Low Power >)I SOC 画 MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 6735芯片外形尺寸图 PIN E CORNER Cccc her Cormon Omenuierg Symbol Mlt.T⊥wx fro sier Eall fish .40 45 1LDER自AL uol thikness SEATING PLANE suTh巴kr 15R ≌dd回 4|0.:550.0D DETA‖L:A Tut thickens 09 TO VIEW C2E fall seand e t 3a.|20 .200.2≤00 SIDE VIEN arkona Ece talera想 Ml是要 010 d t 22888/880 3。8 m cA图 EdI otoe (gckooe 888 ocote8c888。888 9b(n×) Fall callt 4 °g8sM/p828 Edge bal center te centel 12, EI 1200 Ed Mdl Star to Pathom Elg, x s888a8888°888 oroate 日B|○OOC A○○○ ackage in Body size: 12 6x12 6x0 9mm 6°s88;8 Ball pitch: 0. 4mm DETAIL :B Ball diameter: 0. 25mm Ball count: 641 P点E coTToN vEE MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 2015/2/9 T6735 Footprint设计建议 Note MT6735的焊垫使用 copper defined设计方式。(如图一) 钢网开口设计,建议使用0.,25mm方形,并做0.075导R角。(如图二的绿色区域) 打在MT6735焊热上的盲孔(va12)建议使用01/0.25mm(4/10mi),以提升SMT良率。图图二如下图所示,焊垫皆为 copper defined Pad直径0.25mm, solder mask为0325mm。 0.25mm Copper Defined PCB land pad and Copper Defined d Solder mask opening rule Land pad size a 0.25mm9mil Solder mask opening b a+0.075mm a+3mil Pad Pad Solder mask clearance c 0.038mm15mi R0.075 Solder dam d 0.075mm mil Solder mask Ball pitch Te 0.4mm 15mil MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 2015/2/9 MT6735重要信号分布图 eMMc A1 DDR area 17181920212223242526 MEDC MED A RM RAE DQ2 RDC3 0 DA 0 Ds s MDD IDVED GPs GPS RDCLIRDE Fx02 MT6625 SIM1/SIM2 心心区区心心x REx DVDDIDVDD MEDO MAINT DPI PoWeR GND USB CLKT CAMERA To PMIc 5TB AE 圈感图上N1Rx2 UTXD URXC AE BPI BUS s21M1M5M|5 B5I XEPI_5 u513 u59w2 VS5 RFIC FFIC AVSS LTE R LTE R AvS5AFC1 FIC1 BPI B U≤E ENT忑 KM FWM/y ENTI TDIJTCK I5MS AI 1017181920212 LTE TX LTE RX C2K TX/RX BPI BUS MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 2015/2/9 纲目概述封装 MT6735芯片外形尺寸 MT6735 Footprint设计 MT6735重要信号分布图般设计建议叠构( PCB stack-up)建议 Common Rules and via type Placement notes MT6735 fan out High- Speed Digital设计建议 ● LPDDE3 LPDDR2 PDN design 其它设计建议 ●MT6735 RE interface T6169MT6158 MT6328(PMU) MT6625(BT/FM/WiFi/GPS USB/MIPI/ SIM Card/T-Card/ eMMC/Differential Pair Layout Suggestion MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec MT6735PCB叠构 Stack-up建议 PCB之总叠层厚度请勿超过09mm10% 各层铜箔属性丶及中间夹层之厚度和材质请尽量遵照以下建议去规划,以达最佳之电性设计在” Layer definition"中,这里只针对 LPDDR3和cPU做建议。其中“空白”的部分可自行决定,若有空间,可用来做 LPDDR2/3和cPU的PWR/ GND plane的补强其它讯号之" Layer definition请遊照这份 PCB design guide line描述之设计规范进行设计即可。这边共建议了以下几种叠构: 6层1阶介 8层1阶介 8层2阶个孔 8层2介錯昔子 MEDIATER CONFIDENTIALA Copyright O MediaTek Inc. All rights reservec 2015/2/9

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