display_port_1.4_spec.pdfDisplay Port 1.4 spec，英文版

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详细说明：Display Port 1.4 spec，英文版，详细介绍Display Port 1.4协议规范2.2 Isochronous Transport Services in SST Mode 71 2.2. 1 Main Stream to Main-Link Lane Mapping in the Source Device 2.2.2 Stream Reconstruction in the sink device 122 2.2.3 Stream Clock Regeneration 122 2. 2. 4 Main Stream Attribute Data Transport 126 2.2.5 SDP Formats 136 2.2.6 ECC for SDP 209 2.3 AUX CH States and arbitration 215 2.3.1 AUX CH STATES OVerview ...,.,215 2.3.2 Link Layer Arbitration Control 220 2.3.3 Policy Maker AUX Services 220 2.3.4 Detailed DPTX AUX CH State and Event Description ....221 2.3.5 Detailed dPRX aUX CH State and event description 222 2.4 Overview of DP MST Isochronous Transport Service 223 2.4.1 Conncction-oriented Transport 225 242 Layers of DP Isochronous Transport Service∴…………… 227 2. 43 Sideband ch communications 231 2.5 Topology Management Layer 232 2.5.1 Primitives of MST DP Devices and Device Types 233 2.5.2 MST Topologies 236 2.5.3 MST Device Identification 237 2.5.4 Topology Manager and Topology Assistant 239 2.5.5 Topology Discovery 239 2.5.6 Topology maintenance ,非· 240 2.5.7 Topologies with SST-only Source devi ..,.241 2.5.8 Loop HandI 242 2.6 MST Operation 243 2.6.1 Enumeration of path Constraints 248 2.6.2 Link Timing Generation Based on Multi-Stream Transport Packet.... 258 6.3 Symbol Sequence Mapping into VC Payload 259 2.6. 4 Time Slot Count Allocation to vc Payload 270 2.6.5 VC Payload Allocation Synchronization Management 280 2.6.6 ALLOCATE PAYLOAD Timing Sequence .285 2.6.7 Impacts of Various Events on VC Payload ID Table 293 2.6. 8 Robustness requirement 2.6.9 Control Functions, Control Symbols, and K-Code Assignmen 296 297 2.6. 10 Conversion between MST and SST Symbol Mapping......... 298 2.6. 11 MTPH Usages for CP Extension in MST Mode. 300 2.7 Compressed Display Stream Transport Services ....302 2.7. 1 Transport Buffer Model .302 2.7.2 Configuration- Discovery, Enabling, and Disabling 303 2.7.3 Minimum Slices Per Line requirement 306 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 3 of 866 2.8 AUX Transaction Syntax in Manchester Transaction Format 309 2.8.1 Command Definition 2.8.2 AUX Transaction Response/ Reply timeouts 314 2.8.3 Native AUX Request Transaction Syntax. 314 2.8.4 Native AUX Reply Transaction Syntax 315 2.8.5 I2C Bus Transaction Mapping onto AUX Syntax 316 2.8.6 Conversion of I2C Transaction to Native AUX Transaction(Informative).336 2.8.7 12C-over-AUX Transaction Clarifications and Implementation Rules .336 2.9 AUX Services 352 2.9.1 Stream Transport Initiation Sequence 353 2.9.2 Stream Transport Termination Sequence 354 2.9.3 DPCD Field Address Mapping .,.,,,,,,,,.,355 2.9, 4 AUX Link services 477 2.9.5 AUX Device Services 483 2.10 Alternate Scrambler resct for cDP 484 2.10.1 Protocol Differentiation method ....,,,,.,,,484 2.10.2 Symbol Error Rate Measurement Pattern Output(Informative) 484 2. 11 Messaging AUX Client ····, 486 2.11.1 Messaging AUX Client Layers 488 2. 11.2 Message Transaction Layer 490 2.11.3 Sideband MSG Layer 2.11.4 AUX Support for Messaging AUX Client 506 2. 11.5 RAD Updated by MST Devices in the Path 509 2.11.6 Broadcast Message Transactions ·垂 510 2. 11.7 Message Deli 2. 11. 8 Error handling 2. 11.9 Descriptions of Available Message Transaction requests 2. 12 Audio-to-Video and Audio-to-Audio Synchronization............538 2.12.1 Overview 538 2. 12.2 Display port Av Sync Data Block 539 2. 12.3 Delay Compensation 540 2. 13 Global Time Code and Audio Inter-channel sync 546 2.13.1 Global Time Code ..547 2. 13.2 Application of GTC for Audio Inter-channel Synchronization 560 3. 1 Introducti 562 3. 1.1 PHY Layer Functions .563 3. 1.2 Link-phY Layer Interface Signals 564 3. 1. 3 PHY Layer and Link media Interface Signals .565 3. 1.4 Compliance Measurement Points 566 3.1.5 Electrical Signal Definitions ···· 574 3. 1.6 Scrambling 577 3. 1. 7 Symbol Coding and Serialization/De-scrialization .578 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 4 of 866 3.2 DP PWR for Box-to-BoX Display Port Connection 579 3.2.1 DP PWR User Detection Method 581 3.2.2 DP PWR W 581 3.2.3 Inrush Energy 581 3. 2.4 Voltage Droop............... 582 3.2.5 Over-Current Protection 3.3 Hot Plug/Unplug Detect Circuitry 583 3. 4 AUX Channel 585 3.4.1 AUX Channel Logical Sub-block ···: 586 3.4.2 AUX Channel Electrical Sub-block 587 3.5 Main-Link 591 3.5. 1 Main-Link Logic Sub-block .591 3.5.2 Main-Link electrical sub-block 626 3.5.3 ESD and eos Protection 653 3.6 Link Training-tunable PHY Repeater 654 3.6.1 Introduction 654 3.6.2 Signal Routing requirements 657 3.6.3 DPCD Address Mapping for Lt-tunable PhY Repeater 658 3.6. 4 LT-tunable Phy Repeater DPCD Registers 660 3.6.5 AUX Transactions Handling Requirements 662 3.6.6 Link training 667 3.6. 7 Dual mode requirements 680 3.6.8 LT-tunable PhY Repeater Electrical Specification Requirements 681 4.1 Cable-Connector Assembly Specifications(for Box-to-box) 682 1. 1 Cable-Connector Assembly Definition 683 4.1.2 Type of Bulk Cable 687 4.1.3 Impedance profile 688 4.1.4 Insertion Loss and Return Loss 691 4. 1.5 High Bit Rate Cable-Conncctor Assembly Specification 692 4.1.6 Reduced Bit Rate Cable-Connector Assembly Specification 4.2 Connector Specification 706 4.2.1 External Full-size Connector 706 4.2.2 Mini Display port External connector. .719 4.2.3 Panel-side Internal Connector(Informative) 739 5.1 Source Device in SST Mode ···· 748 5.1. 1 Stream Source requirement ...748 5.1.2 Source Device Link Configuration Requirement .752 5.1. 3 Source Device Behavior on Stream Timing change 754 5. 1.4 Source Device Behavior upon HPd Pulse detection .....,,,,,755 5.1.5 Downstream Device DPRX Power Management by a Source Devicc... 756 5.1.6 Source Device Connected to a branch device 5.1.7 Source Device DSC Bitstream Transport and FEC Policy. 757 758 5. 1. 8 MSA Horizontal Blanking Expansion Operation Support 759 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 5 of 866 5.2 Sink device in Sst mode 759 5.2. 1 Stream Sink Requirement 759 5.2.2 Sink Device Link Configuration Requirement .760 5.2.3 Sink Device Behavior on Stream Timing Change 761 5.2.4 Toggling of HPD Signal for Status Change Notification 762 5.2.5 Sink device dPrX power state 763 5.2.6 Sink Device DSC Bitstream Handling and FEC Policy 768 5.3 Branch device in SST-only Mode 769 5.3. 1 EDID Access Handling Requirement 769 5.3.2 Branch Device Link Configuration Requirements 769 5.3.3 Active Protocol Converter Adaptors 770 5.3 4 Link rate and Lane count 780 5.3.5 Forward Error Correction 780 5.4 Source device in Mst Mode 781 5.4.1 Prompting the mst/SsT Capabilities Transition of the Downstream Device 781 5.4.2 Atomic Message Transaction Generation ..781 5.4.3 Power Management 781 5.4. 4 DSC Bitstream Transport and FEC Policy 782 5.5 Sink device in mst mode 782 5.5.1 MST Sink Device with a Single DPRX Upstream-Facing Port..... 782 5.5.2 MST-Capable Sink Device with Multiple DPRX Upstream-Facing Ports. 784 5.6 Branch device in mst Mode .784 5.6. 1 MST-capable Branch Device with a Single DPRX Upstrcam-Facing Port. 784 5.6.2 MST-Capable Branch Device with Multiple DPRX Upstream-Facing Ports 789 5.7 Branch-Sink device in mst mode 789 5.8 Cable-Connector Assembly .789 5.8. 1 Box-to-Box, End-User-Detachable Cable assembly..........789 5.8.2 Embedded and Captive Cable assembly 789 5.8. 3 Active Cable assembly ·: 790 A 1 Audio Stream Components ..791 A 2 Association of Three SDP Types via Packet ID 792 A3 Scheduling of audio Stream SDP transmission ······· 792 A.3.1 Handling of an audio Format Change 794 A 4 Structure of audio stream sdp 794 A.4.11-or 2-Channel audio ......,,.,,,,795 A.4.2 3-to 8-Channel Audio 垂垂垂 795 A 4.3 1-to 2-Channel one Bit audio 796 A 4.4 3-to 8-Channel One Bit audio 796 A. 45 1-to 16-Channel 3d lPCm audio 796 A 4.6 17-to 32-Channel 3D LPCM audio 797 A 4.7 Compressed dST audio 79 A.5 Channel-to-Speaker Mapping 798 A6 Transfer of Sample Frequency Information 799 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 6 of 866 B. 1 Mutual Identification by Source and Sink 800 B 2 IRQ HPD Pulse and Sink Device-Specific IRQ · 800 C 1 Marginal Link Quality 801 C 2 Analysis 801 C 3 Tolerance to Bit errors 802 C.4 Link re-training ..802 C5 Long-term Link Quality Monitoring Guidelines) 803 D1 AUX Parameters 4,·非· 804 D 2 Main-Link parameters 806 D 3 Dual-Dirac Jitter Model 811 G. 1 Background 823 G 2 Problem Statements 823 G 2.1 Problem #1-Sink Connected and Powered, but HPD Low 823 G 2.2 Problem #2-Sink HPD Unplug Event Followed by Plug Event 824 H 1 In-band 3D Stereo Signaling methods 0 H 1.1 MSA MISC 1 Method 829 H.1.2 Video Stream Configuration Packet Method .829 H 2 3D Stereo Display Capability declaration 836 H 2.1 EDID 3D Stereo Display Capability Declaration 837 H 2.2 DisplayID 3D Stereo Display Capability Declaration.........839 H3 Display port Stereo 3d Policy requirements for Interoperability ..840 H.3. 1 Required Support for a Display Port Stereo 3D Sink Device 840 H.3. 2 Required Support for a Display Port Stereo 3D Source Device 843 Self-checking by branch Devices ,,,844 1.2 Merit of QUERY STREAM ENCR YPTION STATUS Message Transaction... 845 1.3 QUERY STREAM ENCRYPTION STATUS Message Transaction Handling in a CP Tree Topology 846 I.3. 1 IDs Provided by Source Device for QUERY STREAM ENCRYPTION STATUS Request message t 846 1.3.2 Stream Status in QUERY STREAM ENCRYPTION STATUS VESA Proposed Display Port(DP) Standard Version 1. 4 dl Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 7 of 866 Reply transaction .848 1.3.3 Stream Status Signature in QUERY STREAM ENCRYPTION STATUS Reply message Transaction 849 1.3.4 USage of Sink Type in Stream Status by a Source Device ..850 I.3.5 Status Q 850 1.3.6 Application of QUERY STREAM ENCRYPTION STATUS Message Transaction to hdcP 853 L 1 Derivation of slice Count re .858 Usage上 xample.… 859 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright C 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 8 of 866 Table 1: Patents 25 Table 2 Main Contributors to Table 3: Revision histo 30 Table 1-1 Acronyms, Initializations, and Abbreviations 44 Table 1-2 Glossary of terms 49 Table 1-3 Reference documents 55 Table 1-4 DP Main-Link Application Bandwidth Table 1-5: Pixel Data Mapping over 4-lane Main-Link .62 Table 2-1 Device Types Covered by this Standard 66 Table 2-2 Topological device Categories ........67 Table 2-3 Control Symbols for Default Framing Mode 74 Table 2-4 Enhanced Framing Mode Control Symbols 76 Table 2-5 Pixel Steering into Main-Link Lanes ..76 Table 2-6 VB-ID Bit Definition 79 Table 2-7 10bpc RGB 30 bits per pixel) 366x768 Packing to a 4-Lane Main-Link, ...82 Table 2-8 8bpc rgb to a 4-Lane Main-Link Mapping .,83 Table 2-9 &bpc rgb mapping to a 2-Lane Main-Link 8 Table 2-10: bpc rGb Mapping to a l-Lane Main-Link 84 Table 2-11: bpc RGB Mapping to a 4-Lane Main-Link 85 Table 2-12: bpc RGB Mapping to a 2-Lane Main-Link ···· 85 Table 2-13: bpc rGb mapping to a l-Lane Main-Link 85 Table 2-14: 10bpc RGB Mapping to a 4-Lane Main-Link ..86 Table 2-15: 10bpc RGB Mapping to a 2-Lane Main-Link 86 Table 2-16: 10bpc RGB Mapping to a l-Lane Main-Link 87 Table 2-17: 12bpc RGB Mapping to a 4-Lane Main-Link 87 Table 2-18: 12bpc RGB Mapping to a 2-Lane Main-Link 87 Table 2-19: 12bpc RGB Mapping to a l-Lane Main-Link 88 Table 2-20: 1 bpc RGB Mapping to a 4-Lane Main-Link 88 Table 2-21: 16bpc RGB Mapping to a 2-Lane Main-Link 89 Table 2-22: 16bpc RGB Mapping to a 1-Lane Main-Link 89 Table 2-23: bpc YCbCr 4: 2: 2 Mapping to a 4-Lane Main-Link Table 2-24 bpc y cbcr 4: 2: 2 Mapping to a 2-Lane main-Link 0 Table 2-25: &bpc Y CbCr 4: 2: 2 Mapping to a 1-Lane Main-Link 90 Table 2-26: 1Obpc YCbCr 4: 2: 2 Mapping to a 4-Lane Main-Link.............. 91 Table 2-27: 1Obpc Y CbCr 4: 2: 2 Mapping to a 2-Lane Main-Link 91 Table 2-28: 10bpc YCbCr 4: 2: 2 Mapping to a 1-Lane Main-Link 91 Table 2-29: 12bpc YCbCr 4: 2: 2 Mapping to a 4-Lane Main -Link..............92 Table 2-30: 12bpc Y CbCr 4: 2: 2 Mapping to a 2-Lane Main-Link. Table 2-31 12bpc YCbCr 4: 2: 2 Mapping to a l-Lane Main-Link Table 2-32: 16bpc YCbCr 4: 2: 2 Mapping to a 4-Lane Main-Link VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. All rights rescrved Pagc 9 of 866 Table 2-33: 16bpc YCbCr 4: 2: 2 Mapping to a 2-Lane Main-Link 93 Table 2-34: 16bpc YCbCr 4: 2: 2 Mapping to a 1-Lane Main-Link 93 Table 2-35: bpc YCbCr 4: 2: 0 Even Lines(Starting with Line O)over Four Main-Link Lanes... 94 Table 2-36: &bpc y cb Cr 4: 2: 0 Odd Lines( starting with line o) over Four Main- Link lanes 94 Table 2-37: bpc Y CbCr 4: 2: 0 Even Lines(Starting with Line 0)over Two Main-Link Lanes Table 2-38: bpc Y CbCr 4: 2: 0 Odd Lines starting with Line 0)over Two Main-Link Lanes 95 Table 2-39: &bpc YCbCr 4: 2: 0 Even Lines(Starting with Line O)over One Main-Link Lane... 95 Table 2-40: &bpc Y CbCr 4: 2: 0 Odd Lines( Starting with Line 0)over One Main-Link Lane 95 Table 2-41: 10bpc YCbCr 4: 2: 0 Even Lines(Starting with Line 0)over Four Main-Link Lanes 96 Table 2-42: 10bpc YCbCr 4: 2: 0 Odd Lines( Starting with Line 0)over Four Main-Link Lanes 96 Table 2-43: 10bpc YCbCr 4: 2: 0 Even Lines(Starting with Line 0)over Two Main-Link Lanes..... 97 Table 2-44: 10bpc YCbCr 4: 2: 0 Odd Lines (Starting with Line 0)over Two Main-Link Lanes... 97 Table 2-45: 10bpc YCbCr 4: 2: 0 Even Lines (Starting with Line 0)over One Main-Link Lane......98 Table 2-46: 10bpc Y CbCr 4: 2: 0 Odd Lines ( Starting with Line 0)over One Main-Link Lane...98 Table 2-47: 12bpc YCbCr 4: 2: 0 Even Lines(Starting with Linc 0)over Four Main-Link Lanes Table 2-48: 12bpc Y CbCr 4: 2: 0 Odd Lines( Starting with Line 0)over Four Main-Link Lanes... 99 Table 2-49: 12bpc Y CbCr 4: 2: 0 Even Lines(Starting with Line 0)over Two Main-Link Lanes.. 100 Table 2-50: 12bpc Y CbCr 4: 2: 0 Odd Lines Starting with Line 0)over Two Main-Link Lancs.. 100 Table 2-51 1 2bpc Y CbCr 4: 2: 0 Even Lines(Starting with Line 0)over One Main-Link Lane 01 Table 2-52: 12bpc YCbCr 4: 2: 0 Odd Lines starting with Line 0)over One Main-Link Lane 101 Table 2-53: 1 6bpc YCbCr 4: 2: 0 Even Lines(Starting with Line 0)over Four Main-Link Lanes.. 102 Table 2-54: 16bpc YCbCr 4: 2: 0 Odd Lines(Starting with Line 0)over Four Main-Link Lanes.. 102 Table 2-55: 16bpc YCbCr 4: 2: 0 Even Lines(Starting with Line 0)over Two Main-Link Lanes.. 103 Table 2-56: 16bpc YCbCr 4: 2: 0 Odd Lines Starting with line 0)over Two Main-Link Lanes.. 103 Table 2-57: 16bpc YCbCr 4: 2: 0 Even Lines(Starting with Line 0)over One Main-Link Lane... 104 Table 2-58 1 6bpc y cbCr 4: 2: 0 Odd Lines( Starting with Line 0)over One Main-Link Lane 104 Table 2-59: bpp Y-only to a 4-Lane Main-Link Mapping 105 Table 2-60: bpp Y-only Mapping to a 2-Lane Main-Link 105 Table 2-61 8bpp y-only Mapping to a 1-Lane Main-Link 105 Table 2-62: 10bpp Y-only Mapping to a 4-Lane Main-Link .106 Table 2-63: 10bpp Y-only Mapping to a 2-Lanc Main-Link ..106 Table 2-64: 10bpp Y-only Mapping to a l-Lane Main-Link ..106 Table 2-65: 12bpp Y-only Mapping to a 4-Lane Main-Link 107 Table 2-66: 12bpp Y-only Mapping to a 2-Lane Main-Link 107 Table 2-67: 12bpp Y-only Mapping to a 1-Lane Main-Link 107 Table 2-68: 16bpp Y-only Mapping to a 4-Lane Main-Link 108 Table 2-69: 16bpp y-only Mapping to a 2-Lane Main-Link ..108 Table 2-70: 16bpp Y-only Mapping to a 1-Lane Main-Link .......,.,108 Table 2-71 bpp raw mapping to a 4-Lane Main-Link ....109 Table 2-72: bpp RaW Mapping to a 2-Lane Main-Link 109 Table 2-73: bpp RaW Mapping to a 1-Lane Main- Link 109 Table 2-74: bpp RaW Mapping to a 4-Lane Main-Link 110 Table 2-75: 7bpp RAW Mapping to a 2-Lane Main-Link 110 Table 2-76: 7bpp raw mapping to a l-Lane Main-Link · 110 Table 2-77: bpp RAW Mapping to a 4-Lane Main-Link......... l11 Table 2-78: bpp RAW Mapping to a 2-Lane Main-Link 111 VESA Proposed Display Port(DP) Standard Version 1. 4 d1 Copyright c 2007-2015 Vidco Electronics Standards Association. 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