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详细说明：STM32L431参考手册RM0394
Contents
3.3.4 Adaptive real-time memory accelerator(ART Accelerator TM)
.80
3.3.5 Flash program and erase operations
82
3.3.6 Flash main memory erase sequences
3.3.7 Flash main memory programming sequences
84
3.4 FLASH option bytes
88
3.4.1 Option bytes description
88
3. 4.2 Option bytes programming
..92
3.5 FLASH memory protection
4
3.5.1 Read protection(RDP)
..94
3.5.2 Proprietary code readout protection(PCROP)
..,97
3.5.3 Write protection(WRP)
98
3.6 FLASH interrupts
3.7 FLASH registers
100
3.7.1 Flash access control register(FLASH ACR)
100
3.7.2 Flash Power-down key register (FLASH_PDKEYR)
10
3.7.3 Flash key register (FLASH KEYR)
101
3.7.4 Flash option key register(FLASH OPTKEYR)
102
3.7.5 Flash status register(FLASH_ SR)
102
3.7.6 Flash control register(FLASH- CR)
,,,,,,104
3.7.7 Flash ECC register(FLASH ECCR)
3.7.8 Flash option register (FLASH OPTR)
.107
3.7.9 Flash PCROP Start address register(FLASH PCROP1SR)
109
3.7.10 Flash PCROP End address register(FLASH_PCROP1ER)
109
3.7.11 Flash WRP area A address register(FLASH WRPlAR)
110
3.7. 12 Flash WRP area B address register(FLASH_ WRP 1BR)
...110
3.7.13 FLASH register map .......
..,,.,112
Firewall(FW)
114
4.1 Introduction
114
4.2 Firewall main features
114
4.3 Firewall functional description
115
4.3.1 Firewall AMBa bus snoop
115
4.3.2 Functional requirements
115
4.3.3 Firewall segments
..116
4.3.4 Segment accesses and properties
117
4.3.5 Firewall initialization
.118
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Contents
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4.3.6 Firewall states
119
4.4 Firewall registers
■
1■
121
4. 4.1 Code segment start address(FW_CSSa)........... 121
4.4.2 Code segment length(FW CSL)
..,121
4.4.3 Non-volatile data segment start address(FW NVDssa
122
4.4.4 Non-volatile data segment length(FW_ NVDSL
122
4.4.5 Volatile data segment start address(FW VDSSA)
.123
4.4.6 Volatile data segment length(FW VDSL
123
4.4.7 Configuration register(FW CR)
..124
4.4.8 Firewall register map
125
Power control (PWR)
126
5.1
Power supplies
126
5. 1.1 Independent analog peripherals supply
128
5.1.2 Independent USB transceivers supply
129
5.1.3
dependent LCD supply
129
5.1.4 Battery backup domain
..130
5.1.5o|t
13
5.1.6VDD12 domain,,.,,,,,,,,,,,,
,,,,,,,132
5.1.7 Dynamic voltage scaling management
..133
5.2 Power supply supervisor
135
5.2.1 Power-on reset(POR)/ power-down reset(PDR)/brown-out reset
(BOR)
135
5.2.2 Programmable voltage detector(PVD)
.,..135
5.2. 3 Peripheral Voltage Monitoring(PVM)
.,,136
5.3 Low-power modes
137
5.3.1 Run mode
144
5.3.2 Low-power run mode(LP run)
144
5.3.3 Low power modes
145
5.3. 4 Sleep mode
146
5.3.5 Low-power sleep mode(Lp sleep
147
5.3.6 Stop 0 mode
148
5.3.7 Stop 1 mode
..150
5.3.8 Stop 2 mode
5.3.9 Standby mode
153
5.3.10 Shutdown mode
156
5.3. 11 Auto-wakeup from low-power mode
.157
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Contents
5.4 PWR registers
158
5. 4.1 Power control register 1(PWR CR1)
5. 4.2 Power control register 2(PWR CR2)
5.4.3 Power control register 3(PWR CR3)
.160
5. 4.4 Power control register 4(PWR CR4
...16
5. 4.5 Power status register 1(PWR SR1)
163
5.4.6 Power status register 2(PWR SR2)
164
5.4.7 Power status clear register(PWR_ SCR)
...,.165
5.4.8 Power Port A pull-up control register(PWR PUCRA)
166
5.4.9 Power Port a pull-down control register(PWR PDCRA)
166
5. 4.10 Power Port B pull-up control register(PWR PUCRB)
167
5.4.11 Power Port B pull-down control register(PWR PDCRB)
167
5.4.12 Power Port C pull-up control register(PWR PUCRC)
..168
5.4.13 Power Port C pull-down control register(PWR_ PDCRC)
.168
5.4.14 Power Port D pull-up control register(PWR PUCRD)
169
5. 4.15 Power Port D pull-down control register(PWR_ PDCRD)
...,.169
5. 4.16 Power Port E pull-up control register(PWR PUCRE)
....,,170
5.4.17 Power Port E pull-down control register(PWR PDCRE
170
5.4.18 Power Port H pull-up control register(PWR PUCRH)
171
5.4.19 Power Port H pull-down control register(PWR_PDCRH)
.171
5. 4.20 PWR register map and reset value table
173
Reset and clock control (RCC)
,,。175
6.1 Reset
,,,,,,175
6.11
D
ower rese
175
6.1.2 System
175
6.1.3 Backup domain reset
176
6.2 Clock
6.2.1 HsE clock
,,,,,181
6.2.2 HSI16 clock
182
6.2.3 MSI clock
183
6.2.4 Hs48 clock
183
6.2.5PLL
.184
6.2.6 LSE clock
185
6.2.7 LSI clock
....185
6.2.8 System clock (SYSCLK) selection
...,185
6.2.9 Clock source frequency versus voltage scaling
186
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Contents
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6.2.10 Clock security system(CSS
186
6.2. 11 Clock security system on LSE
187
6.2.12 ADC clock
.,,,,,,187
6.2.13 RTc clock
187
6.2.14 Timer clock
188
6.2.15 Watchdog clock
188
6.2.16 Clock-out capability
.,189
6.2.17 Internal/external clock measurement with TIM15/TIM16
189
6.2.18 Peripheral clock enable register
(RCC AHBXENR, RCC APBXENRy)
..191
6.3 Low-power modes
.,191
6.4 RCC registers
193
6. 4.1 Clock control register (RCC CR)
..193
6.4.2 Internal clock sources calibration register(RCC ICSCR)
196
6. 4. 3 Clock configuration register(RCC_CFGR)
196
6. 4. 4 PLL configuration register(RCC PLLCFGR)
.198
6.4.5 PLLSAl1 configuration register(RCC PLLSAl1CFGR)
.201
6.4.6 Clock interrupt enable register(RCC_ CIER)
....204
6.4.7 Clock interrupt flag register(RCC CIFR)
206
6.4.8 Clock interrupt clear register(RCC CICR)
....207
6.4.9 AHB1 peripheral reset register(RCC AHB1RSTR)
208
6.4.10 AHB2 peripheral reset register(RCC AHB2RSTR)
209
6.4.11 AHB3 peripheral reset register (RCC_ AHB3RSTR)
.211
6.4.12 AP B1 peripheral reset register 1(RCC APB1RSTR1)
...211
6.4.13 APB 1 peripheral reset register 2(RCC APB1RSTR2)...... 214
6.4.14 APB2 peripheral reset register(RCC APB2RSTR)
215
6.4.15 AHB1 peripheral clock enable register(RCC_ AHBlENR)..... 216
6. 4.16 AHB2 peripheral clock enable register(RCC AHB2ENR)......... 218
6. 4.17 AHB3 peripheral clock enable register(RCC AHB3ENR)
219
6.4.18 APB1 peripheral clock enable register 1(RCC_APBlENR1)
.220
6. 4.19 APB1 peripheral clock enable register 2(RCC APB1ENR2)
222
6. 4.20 AP B2 peripheral clock enable register(RCC_ APB2ENR)..... 224
6.4.21 AHB1 peripheral clocks enable in Sleep and stop modes register
RCC_ AHB1SMENR)............
....225
6. 4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
226
6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
228
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Contents
6. 4.24 AP B1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC APB1SMENR1)
228
6. 4.25 AP B1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC APB1SMENR2
231
6. 4.26 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC APB2SMENR)
233
6. 4.27 Peripherals independent clock configuration register(RCC_ CCIPR). 234
6.4.28 Backup domain control register(RCC_ BDCR)
237
6. 4.29 Control/status register(RCC_CSR)
239
6. 4.30 Clock recovery Rc register(RCC CRRCR)
...241
6.4.31 Peripherals independent clock configuration register(RCC_CCIPR2)242
6. 4.32 RCC register map
242
Clock recovery system(CRS)
247
7.1 Introduction
247
7.2 CRS main features
247
7.3 CRS functional description
248
7.3.1 CRS block diagram
248
7.3.2 Synchronization input
248
7.3.3 Frequency error measurement
249
7.3.4 Frequency error evaluation and automatic trimming
250
7.3.5 CRS initialization and configuration
250
7.4 CRS low-power modes
251
7.5 CRS interrupts
25
7.6 CRS registers
252
7.6. 1 CRS control register(CRS CR)
..252
7.6.2 CRS configuration register(CRS CF GR)
253
7.6.3 CRS interrupt and status register (CRS ISR)
.254
7.6.4 CRS interrupt flag clear register (CRS_ICR)
256
7.6.5 CRS register map
257
General-purpose I/Os(GPIO)
258
8.1 Introduction
258
8.2 GPIO main features
.258
8.3 GPlO functional description
258
8.3.1 General-purpose I/0(GPIO)
8.3.2 10 pin alternate function multiplexer and mapping
26
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Contents
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8.3.3 170 port control registers
262
8.3.4 10 port data registers
262
8.3.5 10 data bitwise handling
262
8.36
GPIO locking mechanism
263
8.3.7 l/0 alternate function input/output
..263
8.3.8 External interrupt/wakeup lines
...263
8.3.9 Input configuration
264
8.3.10 Output configuration
264
8.3.11 Alternate function configuration
265
8.3.12 Analog configuration
8.3.13 Using the HSE or LSE oscillator pins as GPIOs
266
8.3.14 Using the GPIO pins in the Rtc supply domain
266
8.3.15 Using PH3 as GPIO
267
8.4 GPIO registers
267
8.4.1 GPloO port mode register(GPlOX_MODER)(X =A to E and H)... 267
8.4.2 GPIO port output type register(GPIOX_OTYPER)(X=A to E and H)268
8.4.3 GPIO port output speed register(GPlOX_ OSPEEDR
(x=A to E and H
268
8.4.4 GPlO port pull-up/pull-down register(GPIOX PUPDR)
(x=A to E and H
268
8.4.5 GPIO port input data register(GPlOX_iDR)(x=A to E and H)... 269
8.4.6 GPlO port output data register (GPlOx odr)(x=a to E and H).. 269
8.4.7 GPIO port bit set/reset register(GPlOx BSRR)(x =a to E and H).. 270
8.4.8 GPlO port configuration lock register(GPlOx LCKR)
(x =a to E and H)
270
8.4.9 GPIO alternate function low register (GPlOX AFRL
(x=A to E and H)
271
8.4.10 GPIO alternate function high register(GPIOX AFRH)
(x=a to E and H)
272
8.4.11 GPIO port bit reset register(GPIOX BRR)(x=a to E and H)... 273
8.4.12 GPlo register map
274
System configuration controller (SYSCFG)
276
9.1 SYSCFG main features
276
9.2 SYSCFG registers
276
9.2.1 SYSCFG memory remap register(SYSCFG MEMRMP)
276
9.2.2 SYSCFG configuration register 1(SYSCFG CFGR1)
.277
9.2.3 SYSCFG external interrupt configuration register 1
(SYSCFG EXTICR1)
278
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Contents
9.2.4 SYSCFG external interrupt configuration register 2
(SYSCFG EXTICR2
280
9.2.5 SYSCFG external interrupt configuration register 3
(SYSCFG EXTICR3)
9.2.6 SYSCFG external interrupt configuration register 4
(SYSCFG EXTICR4)
28
9.2.7 SYSCFG SRAM2 control and status register(SYSCFG_ SCSR).... 284
9.2.8 SYSCFG configuration register 2(SYSCFG_ CFGR2)
285
9.2.9 SYSCFG SRAM2 write protection register (SYSCFG SWPR)... 286
9.2.10 SYSCFG SRAM2 key register(SYSCFG_ SKR)
286
9.2.11 SYSCFG register map
.287
0
Peripherals interconnect matrix
288
10.1 Introduction
288
10.2 Connection summary
288
10.3 Interconnection details
,,289
10.3.1 From timer(TIM1/TIM2/TIM15/TIM16 to timer(TIM1/TIM2/TIM15/TIM16)
289
10.3.2 From timer(TIM1/TIM2/TIM6/TIM15 and EXti to ADC (ADC1)
290
10.3.3 From ADC (ADC1)to timer(TIM1)
...290
10.3.4 From timer(TIM2/TIM6/TIM7)and EXTI to DAC (DAC1/DAC2)
.290
10.3.5 From HSE, LSE, LSI, MSl, MCO, RtC to timer(TIM2/TIM15/TIM16) 291
10.3.6 From RTC, COMP1, COMP2 to low-power timer(LPTIM1/LPTIM2). 291
10.3.7 From timer (TIM1/TIM2/TIM15)to comparators
COMP1/COMP2)
292
10.3.8 From ADC(ADC1)to ADC(ADC2)
292
10.3. 9 From USB to timer(TIM2
.,,,..292
10.3. 10 From internal analog source to ADC(ADC 1) and OPAMP
(OPAMP1)
293
10.3.11 From comparators(COMP 1/CoMP2)to timers
(TIM1/TIM2/TIM15/TIM16)
293
10.3. 12 From system errors to timers(TIM1/TIM15/TIM16
.294
10.3.13 From timers(TiM16)to IRTIM
294
Direct memory access controller(DMA)
295
11.1 Introduction
295
11.2 DMA main features
,295
11.3 DMA implementation
296
11.3.1 DMA1 and dma2
296
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11.3.2 DMA request mapping
296
11.4 DMA functional description
299
11.4.1 DMa block diagram
..,,,.,.300
11.4.2 DMa transfers
301
11.4.3 dma arbitration
301
11.4.4 DMA channels
302
11.4.5 DMA data width, alignment and endianness
11.4.6 DMA error management
307
11.5 DMA interrupts
308
11.6 DMA registers
308
11.6.1 DMA interrupt status register (DMA ISR)
308
11.6.2 DMA interrupt flag clear register(DMA_IFCR
311
11.6.3 DMA channel x configuration register(DMA_ CCRX)
...312
11.6.4 DMa channel x number of data to transfer register(DMA CNd tRx). 315
11.6.5 DMA channel x peripheral address register(DMA CPARx)
.315
11.6.6 DMA channel x memory address register(DMA CMARX
11.6.7 DMA channel selection register(DMA CSELR)
317
11.6.8 DMA register map and reset values
...317
12
Nested vectored interrupt controller(NVIc)
,,,320
12.1 NVIC main features
320
12.2 Sys Tick calibration value register
320
12.3 Interrupt and exception vectors...........
32
13
Extended interrupts and events controller(EXTI)
325
13.1 Introduction
325
13.2 EXTI main features
325
13.3 EXTI functional description
325
13.3.1 EXTI block diagram
326
13.3.2 Wakeup event management
.326
13.3.3 Peripherals asynchronous Interrupts
13.3.4 Hardware interrupt selection
327
13.3.5 Hardware event selection
327
13.3.6 Software interrupt/event selection
327
13.4 EXTI interrupt/event line mapping
327
13.5 EXTI registers
330
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