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详细说明：SSD2828QL9 SSD2829_Datasheet 关于SSD2828QL9 128脚 官方手册2.1 REFERENCE
2.2 DEFINITIONS…
5.1
UNCTIONAL BLOCKS
5.2 CLOCK AND RESET MODULE
5.3 EXTERNALⅠ NTERFACE……
5.4 PROTOCOL CONTROL UNIT (PCU)
16
5.5 PACKET PROCESSING UNIT (PPU)...
5.6 ERROR CORRECTION CODE/ CYCLIC REDUNDANCY CHECK(ECC/CRC)
5.7 LONG AND COMMAND BUFFERS
5.8 NTERRUPT SIGNAL
5.9 D-PHY CONTROLLER
5.10 ANALOG TRANSCEIVER
SI INTERNAL PLL
1 REGISTER DESCRIPTION REGISTER DESCRIPTION
9.1 LANE MANAGEMENT
9.2 USE CASES….....1111107
9.3 OPERATING MODES
127
10.1 MCU INTERFACE TYPE A FIXED E MODE
145
10.2 MCU INTERFACE TYPE A, CLOCKEDE MODE
147
10.3 MCU INTERFACE TYPE B
148
10. 4 SPI iNTERFaCe 8 BIT 4 Wire
150
10.5 SPl inteRFace &bit 3 Wire
152
10.6 SPI INTERFACE 24 BIT 3 WIRE
156
14.1 MCU INTERFACE(TYPE A)TIMING
165
14.2 MCU INTERFACE(TYPE B) TIMING
143 8 BIT 4 WIRE SPT INTERFACE TIMING
167
14.4 8biT 3 WIRE SPIINTERFACE TIMING
l69
14.5 24BIT 3 WIRE SPI INTERFACE TIMING
∴170
14.6RGBⅠ NTERFACE TIMING……
171
14.7 RESET TIMING
…172
14.8 TX CLK TIMING……
172
19.1 DIMENSION FOR SSD2828T………
179
19.2 MARKING FOR SSD2828T
19.3 CHIP TRAY FOR SSD2828T
l81
TABLE 3-1: ORDERING INFORMATION
TaBLe 6-1: SSD2828T PINOUT DIAGRAM 128 LQFP
TABLE 6-2: SSD2828T PIN ASSIGNMENT
20
TABLE 7-1: MULTIPLEXING SCHEME FOR RGB AND MCU INTERFACE
table 8-1: Ssd2828T REGISTER SUMMARY
TABLE 8-2: DEVICE IDENTIFICATION REGISTER DESCRIPTION
TaBLE 8-3: RGB INTERFACE CONTROL REGISTER 1 DESCRIPTION
2203
TABLE 8-4: RGB INTERFACE CONTROL REGISTER 2 DESCRIPTION
TaBLE 8-5: RGB INTERfAce CONTROL register 3 description
TablE 8-6: RGB Interface CONTRol reGister 4 DesCription
TabLE 8-7: RGB INTERFACE CONTROL REGISTER 5 DeSCrIption
TablE 8-8: RGB INTERFACE CONTROL REGISTER 6 DESCRIPTION
35
TABLE 8-9: CONFIGURATION REGISTER DESCRIPTION
TABLE 8-10: VC CONTROL REGISTER DESCRIPTION
……39
TABLE 8-11: PLL CONTROL REGISTER DESCRIPTION
TaBLE 8-12: PLL CONFIGURATION REGISTER DESCRIPTION
41
TablE 8-13: CLOCK CONTROL REGISTER DESCRIPTION
TABLE 8-14: PACKET SIZE CONTROL REGISTER 1 DESCRIPTION
43
TABLE 8-15: PACKET SIZE CONTROL REGISTER 2 DESCRIPTION
TABLE 8-16: PACKET SIZE CONTROL REGISTER 3 DESCRIPTION
45
TABLE 8-17 GENERIC PACKET DROP REGISTER DESCRIPTION
TAbLE 8-i8: OPERATION CONTROL REGISTER DESCRIPTION
47
TABLE 8-19: MAXIMUM RETURN SIZE REGISTER DESCRIPTION
TABLE 8-20: RETURN DATA COUNT REGISTER DESCRiPtion
.49
TABLE 8-21. ACK RESPONSE STATUS REGISTER DESCRIPTION
TABLE 8-22. LINE CONTROL REGISTER DESCRIPTION
TABLE 8-23 INTERRUPT CONTROL REGISTER DESCRIPTION
table 8-24. INTERRUPT STATUS REGISTER DESCRIPTION
TABLE 8-25, ERROR STATUS REGISTER DESCRIPTION
TADLE 8-266: DELAY ADJUSTMENT REGISTER 1 DESCRIPTION
58
TADLE 8-27 DELAY ADJUSTMENT REGISTER 2 DESCRIPTION
tadle 8-28: DELAY ADJUSTMENT REGISTER 3 DESCRIPTION
60
TABLE 8-29: DELay ADJUSTMENT REGISTER 40/1 DESCRIPTION
TABLE 8-30: DELAY ADJUSTMENT REGISTER 5 DESCRIPtION
…62
TABLE 8-31: DELAY ADJUSTMENT REGISTER 6 DESCRIPTION
TABLE 8-32: HS TX TIMER REGISTER 1 DESCRIPTION
64
TABLE 8-33: HS RX TIMER REGISTER 2 DESCRIPTION
TABLE 8-34: LP TX TIMER REGISTER I DESCRIPTION
66
TABLE 8-35: LP TX TIMER REGISTER 2 DESCRIPTION
TABLE 8-36: TE STATUS REGISTER DESCRIPTION
······
68
TABLE 8-37: SPI READ REGISTER DESCRIPTION
TABLE 8-38: PLL LOCK REGISTER DESCRIPTION
TABLE 8-39: TEST REGISTER DESCRIPTION
TABLE 8-40: TE COUNT REGISTER DESCRIPTION
TABLE 8-41: ANALOG CONTROL 1 REGISTER DESCRIPTION
TABLE 8-42: ANALOG CONTROL REGISTER 2 DESCRIPTION
··
TABLE 8-43: ANALOG CONTROL REGISTER 3 DESCRIPTION
76
TABLE 8-44: ANALOG CONTROL REGISTER 4 DESCRiption
············
TABLE 8-45: INTERRUPT OUTPUT CONTROL REGISTER DESCRIPTION
TABLE 8-46: RGB INTERFACE CONTROL REGISTER 7 DESCRIPTION
··
TABLE 8-47: LANE CONFIGURATION REGISTER DESCRIPTION
TaBLE 8-48: DELAY ADJUSTMENT REGISTER 7 DESCRIPTION
··
TABLE 8-49 PULL CONTROL REGISTER 1 DESCRIPTION
…82
TABLE 8-50: PULL CONTROL REGISTER 2 DESCRIPTION
TABLE 8-51. PULL CONTROL REGISteR 3 DESCRIPTION
TABLE 8-52. CABC BRIGHTNESS CONTROL REGISTER I DESCRIPTION
TABLE 8-53: CABC BRIGHTNESS CONTROL REGISTER 2 DESCRIPTION
87
TABLE 8-54: CABC BRIGHTNESS STATUS REGISTER DESCRIPTION
TABLE 8-55: ENCODER CONTROL REGISTER DESCRIPTION
TABLE 8-56: VIDEO SYNC DELAY REGISTER DESCRIPTION
TABLE 8-57. TRIMMING REGISTER DESCRIPTION
tadle 8-58: GPIOI REGISTER DESCRIPTION
TadLe 8-59: GPIO1 REGISTER DESCRIPTION
TABLE 8-60: DLYAOI REGISTER DESCRIPTION
TABLE 8-61: DLYA23 REGISTER DESCRIPTION
98
TABLE 8-62: DLY Bo1 REGISTER DESCRIPTIO
TABLE 8-63: DL YB23 REGISTER DESCRIPTION
100
101
TABLE8-65:DLYC23 REGISTER DESCRIPTION,……
TABLE 8-66: ACR5 REGISTER DESCRIPTION
103
TABLE 8-67: READ REGISTER DESCRIPTION
105
table 9-1: SSD282&T LANE MANAGEMENT
106
Table 9-2: OPERATION DURING VIDEO MODE BLLP PERIOD
…108
TabLE 9-3, DSI STATE CODE AND DC CHARACTERISTICS
110
TABLE 9-4: DATA LANE MODE ENTERING/EXITING SEQUENCES
TABLE 9-5: START-OF-TRANSMISSION SEQUENCE
l12
TABLE 9-6: END-OF-TRANSMISSION SEQUENCE
table 9-7: MIPI ESCAPE MODE ENTRY CODE
Table 9-8: DATA TYPES FOR PROCESSOR-SOURCED PACKETS
123
Table 9-9: DATA TYPES FOR PERIPHERAL-SOURCED PACKETS
124
TABLE 9-10: PLL SETTING FOR NON-BURST MODE (PLL REFERENCE USING PCLK)
128
TABLE 9-11: PLL SETTING FOR NON-BURST MODE (PLL REFERENCE USING TX CLK)
.128
TabLE 9-12: PLL SETTING FOR BURST MODE
129
TablE 9-13: MIPI ERROR REPORT
138
TABLE 10-1: MCU INTERFACE DATA PIN MAPPING FOR PARAMETER CYCLE
TABLE 11-1: MAXIMUM RATINGS ( VOLTAGE REFERENCED TO VsS)
l60
TABLE 12-1. RECOMMENDED OPERATING CONDITIONS
161
table I3-I. DC CHARACTERISTICS
l62
TABLE 13-2. HS TRANSMITTER DC CHARACTERISTICS
163
TABLE 33-3. LP TRANSMITTER DC CHARACTERISTICS
163
TaBLE 13-4 LP RECEIVER DC CHARACTERISTICS
163
TABLE 14-1: MCU INTERFACE(TYPE A) TIMING CHARACTERISTICS
165
TADLE 14-2: MCU INTERFACE(TYPE B) TIMING CIIARACTERISTICS
TADLE 14-3: 8BIT 4 WIRE SPI INTERFACE TIMING CHIARACTERISTICS
167
TABLE 14-4: 8biT 3 WIRE SPI INTERFACE TIMING CIIARACTERISTICS
169
TADLE 14-5: 24 BiT 3 WIRE SPIINTERFACE TIMING CILARACTERISTICS
170
TADLE 14-6: RGB INTERACE TIMING CIIARACTERISTICS
171
TABLE 14-7. RESET TIMING
172
TABLE 14-8: TX CLK TIMING CHARACTERISTICS
FIGURE 4-1: OVERVIEW O DISPLAY SYSTEM USING SSD2828T
.12
FIGURE 4-2: SSD2828T INTERFACE DIAGRAM
FIGURE 4-3: BLOCK DIAGRAM
4
FIGuRE 5-1: THE CLOCKING SCHEME OF SSD2828T
figure 8-1: TIMING FOR DELAY CALCULATION
FIGuRE 8-2: TIMING FOR DELAY CALCULATION
FIGURE 8-3: TWAKEUP PERIOD DELAY CALCULATION......
FIGurE 8-4: TIMING FOR DELAY CALCULATION
figure 9-1: SSD2828T WITH RGB AND SPI INTERFACE
107
figurE 9-2: SSD282ST WITH MCU INTERFACE
109
figure 9-3: MIPI LINE LEVELS
110
figure 9-4: SWITCHING THE CLOCK LANE BETWEEN HIGH SPEED MODE AND LOW-POWER MODE
FIGurE 9-5: HIGH-SPEED DATA TRANSMISSION IN BURSTS
FIGuRE 9-6: TURNAROUND PROCEDURE
figure 9-7: LOW POWER DATA TRANSMISSION
figure 9-8: TRIGGER- RESET COMMAND IN ESCAPE MODE
117
FIGuRE 9-9: TEARING EFFECT COMMAND IN ESCAPE MODE
118
FIGuRE 9-10: ACKNOWLEDGE COMMAND IN ESCAPE MODE
FIGURE 9-11: TWO DATA TRANSMISSION MODE (SEPARATE, SINGLE)
120
FiGurE 9-12: ONE LANE DATA TRANSMISSION EXAMPLE
120
figure 9-13: TWO LANE HS TRANSMISSION EXAMPLE
120
FIGuRE 9-14: ENDIAN EXAMPLE (LONG PACKET)
121
FIGuRE 9-15: LONG PACKET STRUCTURE
121
FIGURE 9-16: SHORT PACKET STRUCTURE
122
FiGurE 9-17. DATA INDENTIFIER STRUCTURE
122
figure 9-18: 16-BIT PER PIXEL RGB COLOR FORMAT. LONG PACKET FOR MIPI INTERFACE
125
FIGURE9-19:18-BIT PER PIXEI-RGB COLOR FORMAT. LONG PACKET FOR MIPT INTERFACE
figure 9-20: 18-BIT PER PIXEL IN THREE BYTES-RGB COLOR FORMAT. LONG PACKET FOR MIPT INTERFACE
126
figurE 9-21: 24-BIT PER PIXEL -RGB COLOR FORMAT. LONG PACKET FOR MIPT INTERFACE
126
figure 9-22: LLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC PULSES
127
figurE 9-23: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC EVENTS AND BURST
MODE
“自
.128
FigurE 9-24: NON-BURST MODE MIPI STRUCTURD
l30
FIGURE 9-25: BURST MODE MIPI STRUCTURE
l31
FIGuRE 9-26: ACKNOWLEDGEMENT HANDLING AFTER NON-READ COMMAND
136
FIGURE 9-27 ACKNOWLEDGEMENT HANDLING AFTER READ COMMAND
137
Figure 9-28: ILLUSTRATION OF INTERRUPT LATENCY
140
FIGURE 10-1: ILLUSTRATION OF WRITE OPERATION FOR TYPE A. FIXED E MODE INTERFACE
146
FIGURE 10-2: ILLUSTRATION OF READ OPERATION FOR TYPE A FIXED E MODE INTERFACE
146
Figure 10-3: ILLUSTRATION OF WRITE OPERATION FOR TYPE A CLOCKED E MODE INTERFACE............ 147
FIGURE 10-4: ILLUSTRATION OF READ OPERATION FOR TYPE A. CLOCKED E MODE INTERFACE
.148
FIGURE 10-5: ILLUSTRATION OF WRITE OPERATION FOR TYPE B INTERFACE
FIGURE 10-6: ILLUSTRATION OF READ OPERATION FOR TYPE B INTERFACE
149
FiGuRE 10-7: ILLUStRation OF WRITE OpeRation FoR BIT 4 WIRE INTERFACE. ..........................................................150
figure 10-8: ILLUStRatiOn OF REAd OPERATION FoR BIT 4 WIRE INTERFACE
151
FIGURE 10-9: ILLUSTRATION OF WRITE OPERATION FOR 8 BiT 3 WIRE INTERFACE
…152
FIGURE 10-11: ILLUSTRATION OF WRITE OPERATION FOR 24 BIT 3 WIRE INTERFACE
153
156
FIGURE 10-12: ILLUSTRATION OF READ OPERATION FOR 24 BIT 3 WIRE INTERFACE
157
FIGURE 14-1: MCU INTERFACE (TYPE A) TIMING DIAGRAM
∴165
FIGURE 14-2: MCU INTERFACE (TYPE B)TIMING DIAGRAM
166
FIGURE 14-3: 8 BIT 4 WIRE SPI INTERFACE TIMING DIAGRAM
FIGURE 14-4 8 BIT 3 WIRE SPI INTERFACE TIMING DIAGRAM
169
FIGURE 14-5: 24 BIT 3 WIRE SPI INTERFACE TIMING DIAGRAM
170
FIGURE 14-6: RGB INTERFACE TIMING DIAGRAM
171
FIGURE 14-7: TX CLK TIMING DIAGRAM
FIGURE 19-1- PACKAGE INFORMATION
179
FIGURE 19-2-MARKING INFORMATION
FIGURE 19-3- TRAY INFORMATION
The ssd282&T IC is an MIPI master bridge chip that connects an application processor with traditional paralle
LCD interface and an lCd driver with mipi slave interface. The 2828T supports up to 1. 25 Gbps per lane speed
with maximum 4 lanes using both parallel RGB interface and serial SPI interface
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