STM32的Flash操作NULL 博文链接：https://lanxinyuchs.iteye.c

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详细说明：NULL 博文链接：https://lanxinyuchs.iteye.com/blog/1912031PM0075 List of tables List of tables Table 1. Applicable products Table 2. Flash module organization(low-density devices) Table 3 Flash module organization (medium-density devices Table 4. Flash module organization(high-density devices) Table 5 Flash module organization(connectivity line devices 77898 Table 6. Flash memory protection status Table 7 Option byte format 19 Table 8. Option byte organization 20 Table 9. Description of the option bytes 20 Table 10. Abbreviations ..23 Table 11. Flash interface- register map and reset values Table 12. Document revision history 3 Doc D 17863 ReV 2 3 List of figures PM0075 List of figures Figure 1. Programming procedure 13 Figure 2. Flash memory Page Erase procedure Figure 3. Flash memory Mass Erase procedure 4/31 Doc ID 17863 Rev 2 PM0075 Glossary This section gives a brief definition of acronyms and abbreviations used in this document Low-density devices are STM32F101XX, STM32F102XX and STM32F103XX microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes Medium-density devices are STM32F101XX, STM32F102XX and STM32F103XX microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes High-density devices are stM32F101 xx and stm32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes Connectivity line devices are STM32F105xX and STM32F107XX microcontrollers The Cortex-M3 core integrates two debug ports JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group(JTAG) protocol SWD debug port (SWD-DP) provides a 2-pin(clock and data) interface based on the Serial Wire Debug(sWD) protocol For both the jtAG and swd protocols please refer to the cortex M3 Technical Reference Manual Word: data/instruction of 32-bit length e Half word: data/instruction of 16-bit length Byte: data of 8-bit length FPEC (Flash memory program/erase controller): write operations to the main memory and the information block are managed by an embedded Flash program/erase controller(FPEC) IAP (in-application programming): lAP is the ability to re-program the Flash memory of a microcontroller while the user program is running o ICP (in-circuit programming ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWd protocol or the boot loader while the device is mounted on the user application board I-Code this bus connects the instruction bus of the cortex M3 core to the flash instruction interface. Prefetch is performed on this bus o D-Code: this bus connects the D-Code bus(literal load and debug access)of the Cortex-M3 to the flash data Interface Option bytes: product configuration bits stored in the Flash memory OBL: option byte loader AHB: advanced high-performance bus Doc D 17863 ReV 2 5/3 Overview PM0075 Overview Features up to 512 Kbytes of Flash memory Memory organization Main memory block 4 kbits x 64 bits for low-density devices 16 Kbits x 64 bits for medium-density devices 64 kbits x 64 bits for high-density devices 32 Kbits x 64 bits for connectivity line devices Information block 2306 x 64 bits for connectivity line devices 258 x 64 bits for other devices Flash memory interface(FLITE features Read interface with prefetch buffer(2 X 64-bit words ● Option byte Loader Flash Program /Erase operation Read /Write protection Low-power mode 12 Flash module organization The memory organization is based on a main memory block containing 32 pages of 1 Kbyte (for low-density devices), 128 pages of 1 Kbyte(for medium-density devices), 128 pages of 2 Kbyte(for connectivity line devices)or 256 pages of 2 Kbyte(for high-density devices) and an information block as shown in Table 3 and Table 4 Doc ID 17863 Rev 2 PM0075 Overview Table 2. Flash module organization (low-density devices) Block Name Base addresses Size(bytes Page o 0x08000000-0×080003FF 1 Kbyte Page 1 0x08000400-0x080007FF1Kyte Page 2 0×08000800-0×0800OBFF1Kbye Page 3 0xO8000C00-0x08000FFF 1 Kbyte Main memory Page 4 0x08001000-0X080013FF 1 Bite Page 31 0x08007c00-0×08007FFF 1 Kbyte System memory Information block Ox1FFF F000-0x1FFFF7FF2Kbytes Option Bytes OX1FFF F800-Ox1FFF F80F 16 FLASH ACR 0x40022000-0X40022003 FLASH KEYR 0x40022004-0X40022007 FLASH OPTKEYR 0x40022008-0X4002200B Flash memory FLASH SR 0x4002200C-0X4002200F interface FLASH CR 0x40022010-0X40022013 registers FLASH AR 0×40022014.0×40022017 Reserved 0x400220180×4002201B 444444444 FLASH OBR 0x4002201-0x4002201F FLASH WRPR 0x40022020-0X40022023 Table 3. Flash module organization(medium-density devices) Block Name Base addresses Size(bytes Page o 0x08000000-0x080003FF1 Kbyte Page 1 0x08000400-0X080007FF1Kyte Page 2 0x08000800-0X08000BFF1Kbye Page 3 0x08000c00-0X08000FFF 1 Kbyte Main memory Page 4 0×080010000×080013FF1Kbye Page 127 0X0801Fc00-0x0801FFFF 1 Byte System memory 0×1FFE00×1FFFF2 Kbytes Information block Option Bytes OX1FFF F800-OX1FFF F80F 16 Doc D 17863 ReV 2 7/3 Overview PM0075 Table 3. Flash module organization(medium-density devices)(continued) Block Name Base addresses size(bytes) FLASH ACR 0x40022000-0X40022003 4 FLASH KEYR 0x40022004-0X40022007 4 FLASH OPTKEYR 0x40022008-0×4002200B FLASH SR 0x4002200c-0x4002200F Flash memory interface FLASH CR 0x40022010-0×40022013 registers 444 FLASH AR 0x400220140x40022017 Reserved 0x40022018-0X4002201B 4 FLASH OBR 0x4002201-0X4002201F FLASH WRPR 0x40022020-0X40022023 Table 4. Flash module organization(high-density devices) Block Name Base addresses Size(bytes) Page O 0x08000000-0×080007FF2 Kbytes Page 1 0x08000800-008000FFF2 Kbytes Page 2 0x08001000·0X080017FF2 Kbytes Main memor Page 3 0x08001800-0X08001FFF2 Kbytes Page 255 0x0807 F800-0x0807 FFFF 2 Kbytes System memory 0x1FFF F000-Ox1FFF F7FF 2 Kbytes Information block Option Bytes Ox1FFF F800-Ox1FFF F8OF 6 FLASH ACR 0x40022000-0x40022003 FLASH KEYR 0x40022004-0X40022007 FLASH OPTKEYR 0x40022008-0X4002200B 4 FLASH SR 0x4002200c-0X4002200F 4 Flash memory FLASH CR 0x40022010-0X40022013 registers FLASH AR 0x40022014-0x40022017 Reserved 0x40022018-0×4002201B FLASH OBR 0x4002201c-0×4002201F 4 FLASH WRPR 0x40022020-0X40022023 Doc ID 17863 Rev 2 PM0075 Overview Table 5. Flash module organization (connectivity line devices) Block Name Base addresses Size(bytes Page o 0x08000000-0x080007FF2 Kbytes Page 1 0x08000800-0X08000FFF2 Kbytes Page 2 0x08001000·0X080017FF2 Kbytes Main memory Page 3 0×O08001800-0×08001FFF2 Kbytes Page 127 0x0803 F800-0x0803 FFFF 2 Kbytes System memory Ox1FFF B000-0x1FFF F7FF 18 Kbytes Information block Option Bytes Ox1 FFF F800-Ox1 FFF F80F 16 FLASH ACR 0x40022000-0x40022003 FLASH KEYR 0x400220040x40022007 FLASH OPTKEYR 0x400220080X4002200B FLASH SR 0X4002200C-0X4002200F Flash memory interface FLASH CR 0x40022010-0X40022013 registers FLASH AR 0x40022014-0X40022017 Reserved 0×40022018-0×4002201B 444444444 FLASH OBR 0x4002201-0x4002201F FLASH WRPR 0x40022020-0X40022023 The Flash memory is organized as 32-bit wide memory cells that can be used for storing both code and data constants. the flash module is located at a specific base address in the memory map of each STM32F10XXX microcontroller type. For the base address, please refer to the related stm32f 1 0xxx reference manual The information block is divided into two parts System memory is used to boot the device in System memory boot mode. The area is reserved for use by STMicroelectronics and contains the boot loader which is used to reprogram the Flash memory using the USART 1 serial interface. It is programmed by ST when the device is manufactured, and protected against spurious write/erase operations. For further details please refer to AN2606 In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2(remapped), CAN2 (remapped)or USB OTG FS in Device mode(DFU: device firmware upgrade). The USART peripheral operates with the internal 8 MHz oscillator(HSI). The CaN and USB OTG FS, however, can only function if an external 8 MHZ, 14.7456 MHz or 25 MHz clock(HSE)is present. For further details, please refer to AN2662(" STM32F105XX and STM32F107XX system memorybootmode")availablefromwww.st.com ● Option bytes Write operations to the main memory block and the option bytes are managed by an embedded Flash Program/Erase Controller(FPEC). the high voltage needed for Program/Erase operations is internally generated Doc D 17863 ReV 2 9/3 Overview PM0075 The main Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection Page Write Protection Read Protection Refer to section 2, 4 for more details During a write operation to the Flash memory, any attempt to read the Flash memory will stall the bus. The read operation will proceed correctly once the write operation has completed. This means that code or data fetches cannot be made while a write/erase operation is ongoing For write and erase operations on the Flash memory( write/erase), the internal RC oscillator (HSI)must be ON The Flash memory can be programmed and erased using in-circuit programming and in application programming Vote In the low-power modes, all Flash memory accesses are aborted. Refer to the STM32F10xxX reference manual for further information 10/31 Doc ID 17863 Rev 2

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