HSIC 官方最终版文档 High Speed Inter-Chip_1_0 finalHSIC H

文件名称: HSIC 官方最终版文档 High Speed Inter-Chip_1_0 final

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详细说明：HSIC High-Speed Inter-Chip USB Electrical Specification 官方文档High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 The 1.0 revision of the specification is intended for product design. Every attempt has been made to ensure a consistent and implementable specification Implementations should ensure compliance with this revision 1.0 18 September 2007 Initial Release Page 3 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 1.1 General 1.2 Objective of This Supplement…… 国面 1.3 Intended audience 1.4 Relevant documents 55567 1.5 Acronyms and terms 2. 1 HSIC& Standard USB comparison 8 3.1 Discovery∷…… 3.1.1 Power state is ofF 3.1.2 Power state is on, but hsic is not enabled 11 3.1.3 Power state is on. and Hsic is enabled 3.1.4 Power state is ON, HSIC is enabled, and Peripheral signals a CONNECT 3.2 Speed detection .a.::“ 12 3.3 Bus State Signaling 12 3.4 Data Signaling ,, 13 3.5 Bus Keepers in IdlE bus state ∴13 3.6 Hub Support and Mixed Interface Systems 13 Figure 1-Standard USB Host& Peripheral Example .a.:a. Figure 2-HSIC USB Host Peripheral Example 10 Figure 3: Mixed Bus State and Data Transfer Signaling 13 Figure4- HSIC Host& Mixed Interface Hub.……….…… 14 Figure5- Analog Host& Mixed Interface hub……. 14 Figure 6- Host with Analog& HSIC interfaces 15 Table 3-1: Bus State Signaling 12 Page 4 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 applications. Many systems provide a comprehensive set of drivers to support all commonly availabe er USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consume USB peripherals. This enables consumers to purchase and use USB peripherals without having to install a new driver, thus strengthening the popularity of USB. In addition, there are a large number of suppliers of USB silicon, so costs are normally very low for product manufacturers of USB hosts and peripherals As a result of this popularity, it is becoming increasingly attractive to use USB as a chip-to-chip interconnect within a product (without use of external cables or connectors). However, because USB was designed to enable hot-plugging and unplugging of peripherals over cables up to 5 meters in length there are certain power and implementation issues that are not attractive for many chip-to-chip interconnect solutions To better meet the needs of a USB chip-to-chip interconnect, this specification defines a High-Speed Inter-Chip USB supplement to the USB2.0 specification. HSIC accomplishes this by removing the analog transceivers, thus reducing complexity cost and manufacturing risk This supplement provides all of the technical information required to implement a high-Speed Inter-Chip USB solution when used in conjunction with the USB 2.0 Specification Developers and Systems Architects of High-Speed Inter-Chip interfaces that have a maximum circuit trace length of 1 0cm are the intended audience for this document Page 5 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 [USBI Inthecontextofthisdocumentthisspecificallyreferstothefollowingwww.usb.oral parts of the USB 2.0 Specification package The original USB 2.0 specification released on April 27, 2000 Errata to the USB 2.0 specification as of December 7, 2000 Pull-up/pull-down Resistors Engineering Change Notice to the USB 2.0 specification Errata to the USB 2.0 specification as of May 28, 2002 Interface Association Descriptor Engineering Change Notice to the USB 2.0 specification Unicode Engineering Change Notice to the USB 2.0 specification as of February 21, 2005 [ESD76-2] Standard Description of 1.2 V CMOS Logic Devices(Normal Range wwwiedec. org/ Operations) Page 6 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 Double data Rate: describes a signaling technique where data is transferred on both the rising and falling edges of a reference clock (STROBE for HSIC) High Speed Inter-Chip: Used in reference to the 2-signal data/strobe signals defined by this specification Standard Description of 1.2V CMos Logic Devices(Normal Range of Operations ), as described in JESD76-2 The unit of time from a strobe rising edge until the next periodic STROBE rising edge(or falling edge to falling edge) Other acronyms and terms used in this specification are defined in the core specification [USB] Page 7 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 HSIC is a 2-signal (strobe, data source synchronous serial interface which uses 240MHZ DDR signaling to provide High-Speed 480Mbps USB transfers which are 100% host driver compatible with traditional USB cable-connected topologies. Full-Speed(FS)and Low-Speed(LS)USB transfers are not directly supported by the hsic interface(a hSic enabled hub can provide fs and Ls support, as well as IC USB support Major feature and performance highlights are as follows High-Speed 480Mbps data rate only Source-synchronous serial interface No power consumed unless a transfer is in progress Maximum trace length of 10cm No hot Plug-n-Play support, no hot removallattach Signals driven at 1.2V standard LVCMOS levels Designed for low-power applications No high-speed chirp protocol, the HSIC interface is always operated at high-speed SIC is an interface that has been designed to replace a standard USB PHY and USB Cable with an interface that is optimized for circuit board layouts. Figure 1 shows a standard usB implementation of a USB Host and a USB peripheral, Figure 2 shows a similar implementation with an HSIC interface Page 8 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 Note: Link" could be UTML, UTMI, ULPL et cetera USB Host IC(with PHY) USB 2.0 Host aller(EHCD) System USB. PHY Analog front End USB Cable Regulate alog front end USB 2.0 PHY USB Device C(with PH Note: Link* could be UTMI, UTMI, ULPl et cetera Figure 1-Standard USB Host Peripheral Example Page 9 of 16 High-Speed Inter-Chip USB vsn 1.0 September 23, 2007 USB Host IC (HSIC) USB2.0 Hos Controller∈HCD Voltage Regulator L Link* Digital Front End clock source for both Ic Digital Front End DFE) USB 2.0 Device Controller USB Device IC(HSIC) Note: Link"couid be UTMI, UTMI+, ULPL et cetera Figure 2-HSIC USB Host Peripheral Example Page 10 of 16

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