FPGA-based Embedded System Developer’s Guide-CRC (

文件名称: FPGA-based Embedded System Developer’s Guide-CRC (2018).pdf

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详细说明：A. Arockia Bazil Raj - FPGA-based Embedded System Developer’s Guide-CRC (2018).pdfContents List of Figures....... ∴……111 List of tables ............................. xxV List of abbreviations ∴XX1X Preface… ∴XXXV auth XXXIX Part i Basic System Modeling and Programming Techniques 1. Very-Large-Scale Integration Technology: History and Features 1.1 Introduction and preview 1.2 A Review of microelectronics 1.3 Complementary Metal Oxide Semiconductor Technology and Gate 347 Configuration…… 1.4 CMOS Fabrication and layout 1.5 VLSI Design Flow 12 1.6 Combinational and Sequential Circuit Design 14 1.6.1 Combinational logic circuits…… …14 1.6.2 Sequential Logic Circuits ………15 1.7 Subsystem Design and Layout 15 1.8 Types of Application-Specific Integrated Circuits and Their Design Flow...17 1.9 VHDL Requirements and Features 19 Laboratory exercises ..... …21 2. Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language 23 2.1 Introduction and preview. .........................................23 2.2C Design structures...... 24 23 Data Types and Their Conversions…… 34 2.4 Operators and Attributes .45 2.5 Concurrent code∴ ∴50 2.6 Sequential code 2.7 Flip-Flops and Their Conversions 65 2.7.1 Flip-Flops 5 2.7.2 Flip-Flop Conversions 2.8 Data Shift registe 77 2.9 Multifrequency generator ………84 Laboratory exercises 3. Simple system design Techniques 91 3.1 Introduction Q 3.2 Half and Full Adder Q 3.3 Half and full subtractor 3.4 Signed Magnitude Comparator 3.5 Seven-Segment Display Interfacing 104 3.6 Counter Design and Interfacing……..…….…….107 3. 7 Digital Clock Design and Interfacing …115 3.8 Pulse Width Modulation Signal generation .123 3.9 Special System Design Techniques 127 3.9.1 Packages and libraries …127 3.9.2 Functions and procedures .131 Laboratory exercises 134 4. Arithmetic and Logical Programming 135 4.1 Introduction and preview 135 4.2 Arithmetic Operations: Adders and subtractors ∴136 4.2.1 Serial adder 137 4.2.2 Parallel and Pipelined Adders 141 4.2.3 Subtractors .146 4.3 Arithmetic Operations: multipliers 152 4.4 Arithmetic Operations: Dividers 163 4.5 Trigonometric Computations Using the COordinate Rotation Digital Computer( CORDIC) Algorithm 4.6 Multiply-Accumulation Circuit 185 4.7 Arithmetic and Logical Unit 48 Read-Only Memory Design and Logic Implementations.∴…… 188 194 4.9 Random access memory design……… ··, 200 Laboratory exercises Part II Custom Input/Output Peripheral Interfacing 5. Input/Output Bank Programming and Interfacing 207 5.1 Introduction and Preview ∴207 5.2 Opti g 208 5.21 Light-Emitting Diode Displays………… .208 5.2.2 Mult t display 210 5.3 Buzzer control 215 5.4 Liquid Crystal Display Interfacing and Programming 217 5.4.1 Liquid Crystal Display…… 217 5.4.2 Graphical Liquid Crystal Display 223 5.5 General-Purpose Switch Interfacing …28 5.5.1 Dual Inline Package Switch 228 5.5.2 Bidirectional port/, Switch Design………..231 5.5.3 Matrix Keypad Interfacing…… ∴233 5.6 Dual-Tone multifrequency decoder 235 5.7 Optical s ng 238 5.7.1 Infrared Sensors ∴238 5.7.2 Proximity se 242 5.8 Special Sensor Interfacing………… ……244 5.8.1 Passive Infrared Sensor 245 5.8.2 Metal Detecte 248 5.8.3 Light-Dependent resist 251 59 Wind-Speed Sensor Interfacing……………… 255 Laboratory exercises 259 6. System Design with Finite and Algorithmic State Machine Approaches....261 6.1 Introduction and preview …261 6.2 Finite State Machine Design: Moore and Mealy Models 261 621 Moore Finite State Machine design………… 269 6.2.2 Mealy Finite State Machine design.....271 6.2.3 Finite State Machine model Conversion .276 6.3 Code Classifier and binary to binary-Coded Decimal Converters......277 6.3.1 Input Code classifier 278 6.3.2 Binary-to-Binary-Coded-Decimal Converter and Its Arithmetic..282 4 Binary Sequence recognizer 286 6.5 Vending Machine Controller 293 6.6 Traffic Light Controller ∴.30 6.7 Escalator Dice Game and model Train Controller designs .309 6.7.1 Escalator Controller design ∴.309 6.7.2 Dice Game Controller Design 314 6.7.3 Electronic Model Train Controller Design............322 68 Algorithmic State Machine Charts…………… 328 69 Algorithmic State Machine- Based Digital System Design………………………32 Laboratory exercises ∴336 7. Interfacing Digital Logic to the Real World: Sensors, Analog to Digital and Digital to Analog……… 339 7.1 Introduction and preview.……… 339 72 Basics of Signal Conditioning for Sensor Interfacing………….39 7. 2.1 Analog to Digital Conversion 340 2.2 Digital to Analog conversion 341 7.3 Principles of Sensor Interfacing and Measurement Techniques 344 7.3.1 Optical power measurement 344 7.3.2 Temperature Measurement .346 7.3.3 Strain measurement 349 7.3.4 Magnitude Comparator ...........................................350 3.5 ADC0804 Interfacing .351 7.4 Universal Asynchronous receiver-Transmitter design .356 7.4.1 Serial Communication: Data Reading/Writing Using MATLABO.358 7.4.2 UART: Transmitter design 365 7.4.3 Universal asynchronous receiver-Transmitter Receiver design ......371 7.5 Multichannel Data Logging 378 7.5. 1 ADC0808/ADC0809 Interfacing 379 7.5.2ADC0848 Interfacing…… 384 7.5.3 Analog to Digital Converter MAX1112 Interfacing and Seria Data Fetching… 396 7.6 Bipolar Signal Conditioning and Data Logging .399 76.1 Bidirectional Analog to Digital Converter Interfacing………399 7.6.2 Opto-Electronic Position Detector Interfacing 403 7.7 Encoder/Decoder Interfacing for Remote Control Applications 411 7.7.1 Optical Tx/Rx Wireless Control......... 411 7.7.2 Radio Frequency Transmitter/ Receiver Wireless Control 412 7. 8 Pseudorandom binary sequence generator and time-Division Multiple access...................................415 7.8.1 Serial pseudorandom binary sequence generator...........415 8.2 Parallel Pseudorandom Binary Sequence Generator……… 418 7.8.3 Kasami Sequence generator 422 7.8.4 Analog Time Division Multiplexing and M-Array Pulse Amplitude modulation…… 424 7. 9 Signal Generator Design and Interfacing ...........................426 79.1 Low Voltage Digital to Analog Conversion Using DAC0808………426 7.9.2 High-Voltage Digital to Analog Conversion USing DAC7728 ..434 Laboratory exercises 438 Part IIi Hardware Accelerated designs 8. Real-Time clock and interface Protocol Programming…… 8. 1 Introduction and Preview 441 82 Real-Time Clock(DS12887) Interface Programming……… 442 8.3 Inter-Integrated Circuit Interface Programming.........449 84 Two-Wire interface( SHT11 Sensor) Programming…………..456 8.5 Serial Peripheral Interface(SCP1000D) Programming 461 8.6 Global System for Mobile Communications Interface Programming ......467 87 Global Positioning System Interface Programming……………………478 88 Personal System /2 Interface Programming …480 89 Video graphics array Interface Programming………………… 484 Laboratory exercises …492 9. Real-World Control Device Interfacing 493 9.1 Introduction and Preview 9.2 Relay, Solenoid Valve, Opto-Isolator, and Direct Current Motor nterfacing and control.......................................493 9.2.1 Relay control....... 494 9.2.2 Solenoid Valve Control 497 9. 2.3 Opto-Isolator Interfacing 50 9.2.4 Direct Current Motor Control 504 9.3 Servo and bldc motor interfacing and control .....................................508 9.3.1 Servo motor Control 508 9.3.2 Brushless direct Current Motor Control .511 tepper Motor Control.…… 515 9.5 Liquid/ Fuel Level control 518 9.6 Voltage and Current measurement 152 9.7 Power Electronic Device Interfacing and Control 526 9.8 Power Electronics Bidirectional Switch Interfacing and Control……………532 9.8.1 Triac Control 532 9.8.2 Diac Controller ∴536 9. 9 Real-Time Process Controller Design ∴538 Laboratory exercises………… 1544 10. Floating- Point Computations with Very-High-Speed Integrated Circuit Hardware Description Language and Xilinx System Generator (Sys Gen) Tools 547 10.1 Introduction and Preview 547 10.2 Representation of Fixed and Floating-Point binary numbers ∴549 10.2.1 Fixed-Point Number System 549 10.2.2 IEEE754 Single-Precision Floating-Point Number System.....553 10.23IEEE754 Double-Precision Floating-Point Number System…………556 10.2.4 Customized Floating- Point number system ...............................558 10.3 Floating-Point Arithmetic ….561 10.3.1 Floating-Point Addition 10.3.2 Floating-Point Subtraction 565 10.3.3 Floating-Point multiplication......................568 10.3.4 Floating- Point division 573 10.4 Xilinx System Generator(SysGen) Tools 575 10.41 Use and Interfacing Methods of Some Blocksets…………………577 1042 System Design and Implementation Using SysGen Tools………………583 10.5 Fractional-Point Computation using Sysgen tools 594 10.6 System Engine Model Using Xilinx Simulink block sets...... 603 10.7 MATLAB Code Interfacing with Sys Gen Tools 610 10.8 Very-High-Speed Integrated Circuit Hardware Description Language Code Interfacing with SysGen Tools …614 10.9Real- Time Verification and Reconfigurable Architecture Design.……………620 10.9.1 Design Flow for Hardware Co-Simulation... 620 10.9.2 Reconfigurable Architecture Design 622 Laboratory exercises 624 Part Iv Miscellaneous Design and Applications 11. Digital Signal Processing with Field-Programmable Gate Array......627 11. 1 Introduction and preview 627 11.2 Discrete Fourier Transform…………….…….628 113 Digital Finite Impulse response Filter Design………………………641 11.4 Digital Infinite Impulse Response Filter Design 644 11.5 Multirate Signal Processing 650 11.6 Modulo Adder and residual Number arithmetic Systems........ 663 11.6.1 Modulo 2n and 2n-1 Adder Design. 11.6.2 Residue number System................... 665 11.7 Distributed Arithmetic-Based Computations 672 118 Booth Multiplication Algorithm and Design……………………………684 11.9 Adaptive Filter/ Equalizer design 690 Laboratory exercises………… .698 12. Advanced Sys Gen-Based System Desig 12.1 Introduction and preview .701 12.2 Fast Fourier Transform Computation Using Sys gen design .........................701 12.3 Finite Impulse response digital Filter Design ,704 12.4 Infinite Impulse Response Digital Filter Design………….10 12.5 Multiply Accumulation Finite Impulse Response Filter Using SysGen Design…… 712 12.6 Cascaded Integrator Comb Filter Design…….….….….….715 12.7 COordinate Rotation DIgital Computer Design Using Sys Gen Tools....719 12.8 Image Processing Using Discrete Wavelet Transform 722 12. 9 Very-High-Speed Integrated Circuit Hardware Description Language Design Debugging Techniques…..… 727 12.9.1 Chip scope pro analyzer ∴728 12.9.2 Very-High-Speed Integrated Circuit hardware description Language Test-Bench Design 729 12.9.3 Data/Text File Reading/Writing 732 Laboratory exercises 739 13. Contemporary Design and Applications………… 13.1 Introduction and preview 741 13.2 Differential Pulse Code modulation System Design.............741 133 Data Encryption System…… /44 134 Soft Computing algorithms……… 750 13.4.1 Artificial Neural Network …751 1342 Fuzzy Logic Controller…… 753 13.5 Bit Error rate Tester design…………… ··, 755 136 Optical Up/ Down data link…… 761 13.7 Channel Coding Techniques……………… 766 13.7. 1 Linear block code 767 13.7.2 Convolutional Code .769 13.8Pick-and- Place robot controller…… 773 139 Audio codec(AC97) Interfacing…… 775 Laboratory exercises 781 Appendix A ………783 References 791 Index 797 Figures Figure 1.1 Switch models of MOS transistors: nMOS switch(a) and pMOS switch(b)….......……………….7 gure 1.2 Symbol, circuit structure, and truth table of a CmOs inverter......8 Figure 1.3 CMOS configuration of Or (a) and AND(b)gates Figure 1.4 CMOS configuration of NAnd (a)and nOr (b) gates with their truth tables.9 Figure 1.5 Illustrations of CMOS fabrication process Figure 1. vlsi design flow 12 Figure 1.7 Configuration of combinational(a) and sequential(b)circuit.....14 Figure18 Circuit of a full adder…… 16 Figure 1.9 Low-level implementation of a full adder circuit for sum (left)and for carry( right)… 16 Figure 1.10 Classification of ASICs ..17 Figure111 Typical aSiC design flow…… 18 Figure 1.12 VHDL design environment 20 Figure 1.13 Configuration of parallelism using FPGA: x() is I/P samples, Z- is the unit delay element, is the binary multiplier, e is the binary Idder, and Co, Cu. C are filter coefficients 21 Figure 2.1 Symbolic representation of FFs: SR-FF(a, jK-FF(b), D-FF(c), and T-FF ( d).66 Figure 2.2 General design of SR-FF to JK-FF conversion 70 gure 2.3 K-map simplification and circuit diagram for Sr-FF to jK-FF conversion ....71 Figure 2.4 K-map simplification and circuit diagram for JK-FF to SR-FF conversion Figure 2.5 K-map simplification and circuit diagram for Sr-FF to D-FF conversion..73 Figure 2.6 K-map simplification and circuit diagram for D-FF to SR-FF conversion..73 Figure 2.7 K-map simplification and circuit diagram for JK-FF to T-FF conversion .74 Figure 2.8 K-map simplification and circuit diagram for JK-FF to D-FF conversion...75 Figure 2. 9 K-map simplification and circuit diagram for D-FF to JK-FF conversion.76 Figure 2.10 Design of a SISO shift register (a), SIPO Shift register(b), PISO shif register(c), and PIpo shift register(d)…… Figure 2.11 Design of a bidirectional shift register 79 Figure 2.12 Circuit diagram of a 4-bit bidirectional universal shift register Figure 2.13 Clock divider circuit with D-FF (a)and clock divider output(b)...85 Figure 2.14 Counter-based clock divider circuit .86 Figure3.1 Combinational circuit of half(a) and full(b) adder……….92 Figure 3. 2 Construction of a full adder using two half adder circuits(a)and picture of a Cla adder IC74LS83(b).. ∴93 Figure 3. 3 Combinational circuit of a half (a)and full (b) subtractor 96 Figure 3.4 Construction of a full subtractor using two half subtractor circuits Figure35 Construction of a single-bit magnitude comparator……… Figure3.6 Circuit for a4- bit magnitude comparator……… ∴100 Figure 3. 7 Seven-segment display array(a)and different configuration of display modules(b) 105 Figure 3.8 Picture of a seven-segment display decoder ic (a)and a decoder circuit configuration(b) .106 Figure39 Binary4- bit synchronous up counter………… 108 Figure 3.10 Schematic design of digital real-time clock 115 Figure 3.11 Waveform of an in-phase PWM signal 124 Figure 4.1 Schematic diagram of a serial adder .138 Figure42 State transition diagram of a serial adder……… 138 Figure 4.3 General n-bit parallel adder with example addition Figure 4.4 Digital circuit: standard (a)and pipelined(b), input processing in pipelined digital circuit(c), and schematic diagram of a 31-bit pipelined parallel adder(d 144 Figure 4.5 Half subtractor (a), full subtractor using two half subtractors(b), and a typical full subtractor (c) 148 Figure 4.6 Design of a 4-bit parallel subtractor .148 Figure47 Design of a4- bit parallel adder/ subtractor…………………149 Figure 4.8 A 4-bit unsigned binary multiplication(a) and its implementation using half and full adders(b)…… 153 Figure 4.9 Design of an add and shift method-based multiplier........154 Figure410 Fast array multiplier………… …162 Figure4.11 Digital architecture for division operation……… 166 Figure 4.12 Illustration of coordinate rotations...... Figure413 Results of coordinate rotation with different values of x and y……………173 Figure 4.14 Illustration of coordinate rotations 175 Figure 4.15 Profile of the CORDIC scaling factor(Ki) 177 Figure 4.16 Digital design for implementation of CORDIC 178

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