PIC16F19175Microchip /76/85/86等……英文规格书，收藏备用并分享。TAB

文件名称: PIC16F19175

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上传时间: 2019-03-03

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详细说明：Microchip PIC16F19175/76/85/86等……英文规格书，收藏备用并分享。TABLE 1: PIC16(L)F191XX FAMILY TYPES N→z2og-pg3oo9 D 0s0四 g 旦9考 E三≥o F 53v53 oom0oooN PC16(LF19155(4)814256102424 s9oEYYY oo5oom Y Y2/1 96|YN PC16(LF19156(A)162825620482 /2 PC16(L)191754)8/142561024353112 2 2 PC16(LF19176(A)162825620483531122 PC16(LF19185(A)8/1 256 1024 PC16(L)F191864)1628256 43|39 2 PC16()F19195(B)8/14256 1024 45 2 2 22222222 YYYYYYY 2/2 2/2 11111 YYYYYYYY YYYYYYY 2/1 YI184YY 2/1 184YN 2/1 248YN 2/1 248YY 2/1 YYYYYYy 1360YY PC16(L)F19196(B)162825620485945122 360YY PC16LF19197(B)325625640965945122 2/21 2/1 Y|1360YY Note 1: 1 -Debugging integrated on chip Data Sheet Index Unshaded devices are described in this document A. Future Release PIC16(L)F19155/56/75/76/85/86 Data Sheet, 28/40/44/48-Pin B. DS40001873 PIC16(LF19195/6/7 Data Sheet, Full-Featured 64-Pin Microcontrollers Note:Forothersmallform-factorpackageavailabilityandmarkinginformationpleasevisitwww.microchip.com/packagingorcontactyourlocalsalesoffice e。 oo PC16(LF19155/56/75/76/85/86 TABLE 2: PACKAGES 28-Pin28-Pin28-Pin 28-Pin 40-Pin 48-Pin48-Pin 40-Pir 44-Pin Device SPDIP SSOP UQFN UQFN UQFN TQFP SOIC PDIP (4x4) (55) TQFP (6x6)|(7x7) PC16(L)F19155 Ⅹ PC16(LF19156 X X X X P|c16(LF19175 X PC16(L)F19176 PC16(LF19185 X P|c16(L)F19186 Note: Pin details are subject to change FIGURE 1 28-PIN SSOP, SPDIP AND SOIC PIN DIAGRAM FOR PIC16(L)F19155/56 VPP/MCLR/RE3 1 28 RB7/CSPDAT/SEG15 SEG0RA0囗2 27囗RB6 CSPCLK/SEG14 sEG1RA1口3 26□RB5cOM/SEG13 SEG2/RA2「4 25 RB4/COMO SEG3RA3□5 24] RB3/CFLY2/COM6/SEG11 COMO/SEGA/RA46 23 RB2/CFLY1/COM7/SEG10 VBAT/RA5 7 22F RB1/SEG9 VsS凵8 2 RBO/SEG8 了 SEG7/RA7 9 20IVDD SEG6/RA6凵10 19Vss RCO凵11 18□Rc7 NLCD1/COM4SEG23 RC1凵12 17RC6/VLCD2/COM5/SEG22 COM2/SEG18RC2囗13 16ⅥLcD3 sEG19Rc3囗14 15日Rc4/EG20 Note 1: See Table 3 for location of all peripheral functions 2017 Microchip Technology Inc Prelimina DS40001923A-page 4 PC16(LF19155/56/75/76/85/86 FIGURE 2. 28-PIN UQFN PIN DIAGRAM FOR PIC16(L)F19155/56 Nob守 SEG2/RA2 1 21 I RB3/CFLY2/COM6/SEG11 SEG3/RA3 20 RB2/CFLY1/COM7/SEG10 COM3/SEG2/RA4 3 191 RB1/SEG9 18I RBO/SEG8 VSs I5 17 I VDD SEG7/RA716 16 VSS SEG6/RA6 I7 15 RC7/LCD1/COM4/SEG23 L O 寸二OcO=cOu02o0 Note 1: See Table 3 for location of all peripheral functions 2: All VDD and all vss pins must be connected at the circuit board level. Allowing one or more Vss or VDD pins to float may result in degraded electrical performance or non-functionality 3: The bottom pad of the QFN/UQFn package should be connected to Vss at the circuit board level 2017 Microchip Technology Inc Prelimina DS40001923A-page 5 PC16(LF19155/56/75/76/85/86 FIGURE 3: 40-PIN PDIP PIN DIAGRAM FOR PIC16(L)F19175/76 VPP/MCLR/RE3 1 o囗RB7/ CSPDAT/SEG15 SEGO/RA0囗2 39□RB6/ CSPCLK/SEG4 SEGl/RA1[3 38 RB5/COM1/SEG13 SEG2/RA2∏4 37 RB4/COM0 EG3/RA3 5 36 RB3/CFLY2/SEG11 COM3SEG4RA4囗6 35 RB2/CFLY1/SEG10 VBAT/RA57 34□RB1/SEG9 SEG32/REo8 33凵RB0SEG8 COM6/SEG33/RE1[9 32VDD COM7/SEG34RE2囗10 31口ss 30RD7/SEG31 29□RD6/SEG30 SEG7RA7囗13 囗RD5/SEG29 SEG6/RA6 14 27]RD4/SEG28 RCO| 15 26RC7/LCD1/SEG23 RC1[16 25RC6/LCD2/SEG22 cOM2SEG18RC2凵17 24囗VLcD3 SEG19/RC3∏18 23RC4/SEG20 SEG24/RD0凵19 22 RD3/COM4/SEG27 SEG25/RD1∏20 21 RD2/COM5/SEG26 Note: See Table 4 for the pin allocation tables FIGURE 4 40-PIN UQFN (5X5X0, 5)PIN DIAGRAM FOR PIC16(L)F19175/76 ao c OuOO 导男88萵88两 SEG23MLCD1/RC7■1 R SEG28/RD42 29 RA6/SEG6 SEG29/RD5 3 28[ RA7/SEG7 SEG30/RD6■4 27I VsS SEG31/RD7 5 26IVDD VsS■6 25[ RE2/COM7/SEG34 /DD7 24[ RE1/COM6/SEG33 SEG8/RBO■8 23[ REO/SEG32 SEG9/RB1 19 22 I RA5/VBAT SEG 10/CFLY1/RB210 21RA4C○M3SEG4 品-2 zoO Note: See Table 4 for the pin allocation tables 2017 Microchip Technology Inc Prelimina DS40001923A-page 6 PC16(LF19155/56/75/76/85/86 FIGURE 5. 44-PIN TQFP PIN DIAGRAM FOR PIC16(L)F19175/76 ccOucaO=>oOm Q0 Ou uoO 守守导男883 SEG23/LCD1/RC7II11 33口NC SEG28/RD4[ 2 32LT RCO SEG29/RD5 31 H RA6/SEG6 SEG30/RD6「T4 30□RA7/SEG7 SEG31/RD7DI5 29 HIT VsS Ussd 28 VDD VDD[I7 27 LI RE2/COM7/SEG34 SEG8/RBODI8 26□RE1COM6/SEG33 SEGS/RB1[ 9 5IT REO/SEG32 SEG10/CFLY1/RB2D 10 24口口RA5VBAT sEG!CFLY2/RB3[口11 23□RA4COM3/SEG4 Ss98; 2"品 g男出 NOu O=寸Ou0 OoO Note: See Table 4 for the pin allocation table 2017 Microchip Technology Inc Prelimina DS40001923A-page 7 PC16(LF19155/56/75/76/85/86 FIGURE 6. 48-PIN TQFP/UQFN PIN DIAGRAM FOR PIC16(L)F19185/86 ocOu≌寸O Ouoo>6O C >CCC Ccc o c 88 SEG23∧LCD1/Rc7 36 HT RFO/SEG40 sEG28/RD4匚2 35RC1 sEG29/RD5[山3 34口Rc0 SEG30/RD6 33 IT RAG/SEG6 SEG31/RD7 5 32 IT RA7/SEG7 Vss[山6 31 T VSS VDD匚7 sEG8RB0[山8 29 HIT RE2/COM7/SEG34 SEG9/RB1[II 9 28 IT RE1/COM6/SEG33 SEG10/CFLY1/RB2 DIT 10 27 IT REO/SEG32 SEG11CFLY2/RB3[山11 26 IT RA5/VBAT SEG44/RF4 25口RA4COM3/SEG4 只P9988 自≡ 出8 g出出宫 O寸Ou0 Note 1: See Table 5 for location of all peripheral functions 2: QFN package orientation is the same. No leads are present on the QFn package 2017 Microchip Technology Inc Prelimina DS40001923A-page 8 PIN ALLOCATION TABLES N→z2og-pg3oo9 TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(LF19155/56) go0.00aa05 zgs°N 59o oaoos9oN E93 o3式 8 RAO 227 ANAO ClINO- CLCINo() SEGO IOCAO C2INO RA1 ANA1 C2|N1- CLCIN11) SEG1IOCA1 RA2 4 ANA2 ClINO+ C2INO+ I DAC1OUT1 SEG2 IOCA2 RA3 2 ANA3 VREF+C1IN1 DAC IREF+ SEG3 lOCA3 ANA4 TOCKI) SEG4 IOCA4 COM3 ss(1) IOCA5 VBAT RA6107 CLKOUT ANA6 SEG6 IOCA6 RAZ 9 ANA SEG7 IOCA7 CLKIN RBO 2118 NBO C2IN1+ ZCD CWG1IN(1) SEG8 IOCBO INTPP e。 RB1 2219 AnB 1 c1|N3 SCL C2N3 sDA1,3,45,6) SEG9 OCB1HIB1Y SCL SEG10 RB2 ANB sDA1,345,6) COM7IOCB2 CFLY1 SEG11 RB3 24|21 anB c1|N2 C2|N2 COM6 lOCB3 CFLY2 ANB RB4 252 ADCACT(1) COMO IOCB4 RB5 2623 ANB5 T1G() SEG13 COM1 IOCB5 Note 1: This is a PPs remappable input signal. the input function may be moved from the default location shown to one of several other PoRTX pins 2: All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTX pin options 3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPs input and pps output registers 4: These pins are configured for IC logic levels. PPS assignments to the other pins will operate but input logic levels will be standard TtL/ST as selected by INlcVL register, instead of the lC specific or US input buffer thr 5: These are altemative 12C logic levels pins 6: In IC logic levels configuration, these pins can operate as either SCL and SDA pins oo TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F19155/56)(CONTINUED) N2o-0ooo9 0.0maa054 zLCE°N o=9 oawv9Q TX2(1) RB62724 ANB CK2(1) CLCIN2(1) SEG14 IOCB6 YCDCLK ICSPCLK RX2(1) RB72825 ANB DAC1OUT2 DT2(1) CLCIN3(1) SEG15 IOCB7 Y CDDAT ICSPDAT RC0118 TICK ( 1) SMTWIN1(1) Y SOSCO SMTSIG1(1) RC1129 T4IN(1) CCP2(1) lOCC1 Y SOSC RC2 1310 ANC2 CCP1(1) COM2 SEG18 lOCC2 RC31411 ANC T2IN() ScK(1) SCL(1,3, 4) SEG19IOCC3 SDI(1) RC41512 ANC SDA(1, 3, 4) SEG20IOCC4 TX1(1) RC61714 ANC CK1 (1) SEG22 lOCC6 VLCD2 Rx1(1 SEG23 e。 RC71815 ANC DT1(1) COM4 IOCC7 VLCD1 RE3 IOCE3 MCLR VLCD31613 CD3 7 Vss 85 1916 TX1 DT1 OUT(2) ADGRDA ClOUT TMRO CCP1 PWM3 CWG1B SCK ADGRDB C 2OUT CCP2 PWM4 CWG1C TX2 CLClOUT RTCC CWG1D SDA DT2 Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other Portx pins 2: All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more Portx pin options 3: This is a bidirectional signal For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers 4: These pins are configured for 12C logic levels. Pps assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by INLCVL register, instead of the 2c specific or SMBUS input buffer thresholds 5: These are altemative l-C logic levels pins oo 6: In |2C logic levels configuration, these pins can operate as either SCL and SDA pins

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