LATTICE-ECP3-datasheet 莱迪斯ecp3器件系列的数据手册The Lattice

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详细说明：LATTICE-ECP3-datasheet 莱迪斯ecp3器件系列的数据手册The LatticeECP3TM(EConomy Plus Third generation) family of fpga devices is optimized to deliver high perfor- mance features such as an enhanced dsP architecture, high speed serdeS and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications The LatticeECP3 device family expands look-up-table(LUT)capacity to 149K logic elements and supports up to 586 user I/Os. The LatticeeCP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel 1O standards The LatticeeCP3 FPGa fabric is optimized with high performance and low cost in mind the Lattice ecP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib uted and embedded memory, Phase Locked Loops(PLLs), Delay Locked Loops(DLLs), pre-engineered source synchronous IO support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities The pre-engineered source synchronous logic implemented in the Lattice ECP3 device family supports a broad range of interface standards, including ddR3, XGMIl and 7: 1 LVDS The LatticeeCP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler ance and low transmit jitter allow the serdes plus pcs blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha- sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media The LatticeeCP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa bility, bit-stream encryption, and TransFR field upgrade features The Lattice Diamond m and isplEVER design software allows large complex designs to be efficiently imple mented using the Lattice ECP3 FPGa family. Synthesis library support for Lattice ECP3 is available for popular logic synthesis tools. Diamond and isplEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing and back-annotate it into the design for timing verification Lattice provides many pre-engineered IP (Intellectual Property) modules for the Lattice ECP3 family By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity 1-2 ■■■ ■■■ ■■ Lattice 日■ Semiconductor ■■■■"c。 rporation Each Lattice ECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells(PIC). Inter spersed between the rows of logic blocks are rows of sysMEMTM Embedded Block RAM(EBR) and rows of sys DSP TM Digital Signal Processing slices, as shown in Figure 2-1. The Lattice ECP3-150 has four rows of DSP slices all other LatticeECP3 devices have two rows of dSP slices. In addition, the Lattice EC P3 family contains SERDES Quads on the bottom of the device There are two kinds of logic blocks, the Programmable Functional Unit(PFU)and Programmable Functional Unit without RAM(PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFf blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two dimensional array. Only one type of block is used per row The LatticeeCP3 devices contain one or more rows of sysMEM EBR blocks. SysMEM EBRs are large, dedicated 18Kbit tast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, Lattice ECP3 devices contain up to two rows of dSP slices. Each dSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities The LatticeECP3 devices feature up to 16 embedded 3. 2Gbps SERDES (Serializer/ Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding /decoding, polarity adjust and elastic buffer logic. Each group of four SERDES channels, along with its Physical Coding Sub-layer(PCs)block, creates a quad. The func- tionality of the serdES/Pcs quads can be controlled by memory cells set during device configuration or by regis ters that are addressable during device operation. The registers in every quad can be programmed via the SERDES Client Interface(SCI). These quads(up to four)are located at the bottom of the devices Each Pic block encompasses two PlOs(PIO pairs) with their respective sysl/o buffers. The sysl/o buffers of the LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of lo standards In addition, a separate 0 bank is provided for the programming interfaces. 50% of the Plo pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The Pic logic also includes pre-engi- neered support to aid in the implementation of high speed source synchronous standards such as XGMll, 7: 1 LVDS, along with memory interfaces including DDR3 Other blocks provided include PLLS, DLLs and configuration functions. The Lattice ECP3 architecture provides two Delay Locked Loops(DLLs)and up to ten Phase Locked Loops(PLLs). The PLL and dLL blocks are located at the end of the ebr/dsp rows The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located toward the center of this EBR row. Every device in the Lattice ECP3 family sup ports a sysCoNFIGTM port located in the corner between banks one and two, which allows for serial or parallel device configuration In addition, every device in the family has a jTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LatticeECP3 devices use 1.2V as their core voltage 2011LatticeseMiconductorCorp.AllLatticetrademarksregisteredtrademarkspatentsanddisclaimersareaslistedatwww.latticesemi.com/legal.Allotherbrand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice DS 1021 Architecture 01.8 sys syslog Configuration Logic Bank o Bank 1 Dual-boot, Encryption and Transparent Updates JTAO On-chip oscillat 評能 Pre-engineered Source Synchronous Support syscO sysIoDDR3-800Mbps Bank Bank Generic-Up to 1Gbps Enhanced dsp Slices: Multiply, Accumulate and aLU 畾暗畾郾 sysCLOCK Plls dlls: and clock Alignmen Flexible syslo: 11 LVCMOS HSTL Up to 486 1Os sysMEM Block RAM: 18Kbit Flexible Routing Optimized for speed and routabili Programmable SERDESIPCSISERDES/PCS SERDES/PCS ISERDES/PCS Function Units CH 1 CH O Up to 149K LUTS syslo Bank 6 syslo Bank 3 3. 2Gbps SERDES Note: There is ng bank 4 or bank 5 in LatticeECP3 device The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions EXcept where necessary, the remain- der of this data sheet will use the term pfu to refer to both pfu and pff blocks Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains tWo LUTs. All the interconnections to and from PFU blocks are from routing There are 50 inputs and 23 outputs associated with each pfu block 2-2 ▲A▲ A FF FF FF FF FF Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only For PFUs, Slice 0 through Slice 2 can be configured as distributed memory, a capability not available in the PFF Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition each pfu contains logic that allows the luts to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions(programmable as synchronous asynchronous), clock select, chip-select and wider RAM/ROM functions Slice0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice12 LUT4s and 2 Registers Logic, Ripple. RAM, ROM 2 LUT4s and 2 RegistersLogic, Ripple, ROM Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 3 2 LUT4s Logic, ROM 2 LUT4s LogIc, ROM Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi- tive/negative and edge triggered or level sensitive clocks Slices 0, 1 and 2 have 1 4 input signals: 13 signals from routing and one from the carry-chain(from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain(to the adjacent PFU). slice 3 has 10 input signals from routing and four signals to routing Table 2-2 lists the signals associated with Slice 0 to Slice 2 2-3 FCO To Different Slice/PFU SLICE FXB OFX1 FXA A B1 F/SUM D1 LUT4 8 CARRY FFY To Routing From Routing OFXO AO O BO LUT4 CARRY‘FsUM ED CE CLK LSR Not in slice 3 FCI From Different slice/PFU For Slices 0 and 1, memory control signals are generated from slice 2 as follows WCK is CLK RE is from lSR DI[3: 2] for Slice 1 and DI[1: 0] for Sliced data from Slice 2 WAD [A: D] is a 4-bit address from slice 2 LUT input Input Data signal AO,B0,CO,Do Inputs to LUT4 Input Data signal Al,B1,C1, D1 Inputs to LUT4 InputMulti-purpose Multipurpose Input Input Multl-purpose M1 Multipurpose input Input Control signal CE Clock enable Input Control signal LSR Local set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FC Fast Carry-in Input Inter-slice signal FⅩA Intermediate signal to generate LUT6 and LUT7 Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7 Output Data signals F0.F1 LUt4 output register bypass signals Output dIs Data signal Q0. Q1 Register outputs Output Data signals OFXO Output of a LUt5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT8 MUX depending on the slice OutputInter-PFU signal FCO Slice 2 of each P FU is the fast carry chain output See Figure 2-3 for connection details 2. Requires two PFUs Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM In this mode, the LUts in each slice are configured as 4-input combinatorial lookup tables. a LUt4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table Since there are two LUT4s per slice, a LUt5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUTB requires more than four slices Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func tions can be implemented by each slice · Addition2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control · Up counter2bit · Down counter2-bit Up/Down counter with asynchronous clear Up/Down counter with preload(sync) Ripple mode multiplier building block Multiplier support Comparator functions of a and B inputs a greater-than-or-equal-to B A not-equal-to B A less-than-or-equal-to B Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con- figuration also referred to as ccU2 mode) two additional signals, Carry Generate and Carry propagate, are gener ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices In this mode, a 16x4-bit distributed single port RAM(SPR)can be constructed using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit pseudo dual port RAM(PDPR)memory is created by using one Slice as the read-write port and the other companion slice as the read-only port LatticeECP3 devices support distributed memory initialization The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP3 devices, please see TN1179, Lattice ECP3 Memory Usage Guide Number of slices 3 3 Note: SPR= Single Port RAM, PDPR= Pseudo dual Port RAM 2-5 ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode Preloading is accomplished through the programming interface during PFU configuration or more information, please refer to TN1179, LatticeECP3 Memory Usage Guide There are many resources provided in the LatticeECP3 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect(routing) segments The LatticeECP3 family has an enhanced routing architecture that produces a compact design The diamond and ispLEVER design software tool suites take the output of the synthesis tool and places and routes the design The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the LatticeECP3 family support two to ten full-featured General Purpose PLls The architecture of the Pll is shown in Figure 2-4. a description of the Pll functionality follows CLKi is the reference frequency (generated either from the pin or from routing) for the PLL clKi feeds into the Input Clock Divider block. The CLK FB is the feedback signal (generated from CLKOP, CLKos or from a user clock pin/logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre quency Both the input path and feedback signals enter the phase Frequency detect Block(PFD) which detects first for the frequency, and then the phase, of the ClKI and CLKFB are the same which then drives the voltage Controlled Oscillator(VCO)block. In this block the difference between the input path and feedback signals is used to control the frequency and phase of the oscillator a LOCK signal is generated by the vco to indicate that the vco has locked onto the input clock signal. In dynamic mode, the PLl may lose lock after a dynamic delay adjustment and not relock until the tLock parameter has been satisfied The output of the vCo then enters the CLKoP divider. The CLKoP divider allows the vco to operate at higher fre quencies than the clock output (CLKoP), thereby increasing the frequency range. the Phase/duty cycle/duty Trim block adjusts the phase and duty cycle of the CLKOs signal. The phase/duty cycle setting can be pre-programmed or dynamically adjusted. A secondary divider takes the CLKoP or CLKos signal and uses it to derive lower fre quency outputs(CLKOK) and CLKOK2)and Phase/Duty select(CLKOS ) are fed to the clock distribution networ econdary dividers(CLKOK The primary output from the ClOp divider(CLKoP)along with the outputs from the The PLL allows two methods for adjusting the phase of signal. The first is referred to as Fine Delay Adjustment This inserts up to 16 nominal 125ps delays to be applied to the secondary PLL output. The number of steps may be set statically or from the FPGa logic. The second method is referred to as Coarse Phase Adjustment. This allows the phase of the rising and falling edge of the secondary pll output to be adjusted in 22. 5 degree steps The number of steps may be set statically or from the FPGa logic FDAJ3. 0 WRDEL :3 CLKI CLKI Duty cycle/ Divide Duty Trim F PFD Loop Filter Divider CLKOP CLKFB→ CLKFB Duty Trim CLKOK Divider RSTK RST DRPAI3: O DFPAll3: 0 Table 2-4 provides a description of the signals in the PLL blocks CLKI Clock input from external pin or routing CLKFB PLL feedback input from CLKOP, CLKOS, or from a user clock (pin or logic RST 1"to reset PLL counters, VCO, charge pumps and M-dividers RSTK 1 to reset K-divider WRDEL DPA Fine Delay Adjust input CLKOS o PLL output to clock tree(phase shifted/duty cycle changed CLKOP oPLL output to clock tree(no phase shift) CLKOK o PLL output to clock tree through secondary clock divider CLKOK2 O PLL output to clock tree( CLKoP divided by 3) LOCK O|“1” indicates PLL LoCK to CLK FDA 3: 0 I Dynamic fine delay adjustment on CLKOS output DRPA[3: 0 Dynamic coarse phase shift, rising edge setting DFPAI3: 0 I Dynamic coarse phase shift, falling edge setting In addition to PLLS, the Lattice ECP3 family of devices has two DLLs per device CLKI is the input frequency (generated either from the pin or routing) for the DLL clKi feeds into the output muxes block to bypass the DLL, directly to the DELAY CHAIN block and(directly or through divider circuit)to the reference input of the phase detector(PD)input mux. the reference signal for the pd can also be generated from the delay Chain signals. The feedback input to the Pd is generated from the ClKFB pin or from a tapped signal from the Delay chain The Pd produces a binary number proportional to the phase and frequency difference between the reference and feedback signals Based on these inputs, the aLu determines the correct digital control codes to send to the delay 2-7

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