204-Pin DDR3 SDRAM Unbuffered SODIMM Design SpecificationJEDEC Standard No 21c Page42018-3 Decoupling Capacitor Guideline 28 Differential Clock Net structures 29 Clock Net Wiring CK[1: 0], CK[1: 0](Raw Cards A, c) 29 Clock Net Wiring CK[O], CK[O](Raw