This application note describes how to interface the Virtex®-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC Standard No. 204A (JESD204A) Serial Interface for Data Converters
This application note describes how to interface the Virtex®-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC Standard No. 204A (JESD204A)
The Xilinx® LogiCORE™ IP JESD204 core
implements a JESD204B interface supporting
line rates from 1 Gb/s to 12.5 Gb/s(1). The
JESD204 core can be configured as a
transmitter or receiver
xilinx fpga gt wizard serdes手册 用于Xilinx开发查看sXL|NⅩ
ALL PROGRAMMABLEN
Reset Sequence Modules for GTH and GTP Transceivers
87
Example design descr iption for gTZ Transceivers.................... 87
Known limitations of the gtz wizard
·····:::.:.:·····.·
